| Marek Vasut | d1fcb36 | 2011-11-08 23:18:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Freescale i.MX28 USB PHY Register Definitions |
| 3 | * |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 5 | * on behalf of DENX Software Engineering GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | #ifndef __REGS_USBPHY_H__ |
| 24 | #define __REGS_USBPHY_H__ |
| 25 | |
| 26 | struct mx28_usbphy_regs { |
| 27 | mx28_reg(hw_usbphy_pwd) |
| 28 | mx28_reg(hw_usbphy_tx) |
| 29 | mx28_reg(hw_usbphy_rx) |
| 30 | mx28_reg(hw_usbphy_ctrl) |
| 31 | mx28_reg(hw_usbphy_status) |
| 32 | mx28_reg(hw_usbphy_debug) |
| 33 | mx28_reg(hw_usbphy_debug0_status) |
| 34 | mx28_reg(hw_usbphy_debug1) |
| 35 | mx28_reg(hw_usbphy_version) |
| 36 | mx28_reg(hw_usbphy_ip) |
| 37 | }; |
| 38 | |
| 39 | #define USBPHY_PWD_RXPWDRX (1 << 20) |
| 40 | #define USBPHY_PWD_RXPWDDIFF (1 << 19) |
| 41 | #define USBPHY_PWD_RXPWD1PT1 (1 << 18) |
| 42 | #define USBPHY_PWD_RXPWDENV (1 << 17) |
| 43 | #define USBPHY_PWD_TXPWDV2I (1 << 12) |
| 44 | #define USBPHY_PWD_TXPWDIBIAS (1 << 11) |
| 45 | #define USBPHY_PWD_TXPWDFS (1 << 10) |
| 46 | |
| 47 | #define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 |
| 48 | #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) |
| 49 | #define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) |
| 50 | #define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) |
| 51 | #define USBPHY_TX_TXENCAL45DP (1 << 21) |
| 52 | #define USBPHY_TX_TXCAL45DP_OFFSET 16 |
| 53 | #define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) |
| 54 | #define USBPHY_TX_TXENCAL45DM (1 << 13) |
| 55 | #define USBPHY_TX_TXCAL45DM_OFFSET 8 |
| 56 | #define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) |
| 57 | #define USBPHY_TX_D_CAL_OFFSET 0 |
| 58 | #define USBPHY_TX_D_CAL_MASK 0xf |
| 59 | |
| 60 | #define USBPHY_RX_RXDBYPASS (1 << 22) |
| 61 | #define USBPHY_RX_DISCONADJ_OFFSET 4 |
| 62 | #define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) |
| 63 | #define USBPHY_RX_ENVADJ_OFFSET 0 |
| 64 | #define USBPHY_RX_ENVADJ_MASK 0x7 |
| 65 | |
| 66 | #define USBPHY_CTRL_SFTRST (1 << 31) |
| 67 | #define USBPHY_CTRL_CLKGATE (1 << 30) |
| 68 | #define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) |
| 69 | #define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) |
| 70 | #define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) |
| 71 | #define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) |
| 72 | #define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) |
| 73 | #define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) |
| 74 | #define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) |
| 75 | #define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) |
| 76 | #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) |
| 77 | #define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) |
| 78 | #define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) |
| 79 | #define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) |
| 80 | #define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) |
| 81 | #define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) |
| 82 | #define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) |
| 83 | #define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) |
| 84 | #define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) |
| 85 | #define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) |
| 86 | #define USBPHY_CTRL_RESUME_IRQ (1 << 10) |
| 87 | #define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) |
| 88 | #define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) |
| 89 | #define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) |
| 90 | #define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) |
| 91 | #define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) |
| 92 | #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) |
| 93 | #define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) |
| 94 | #define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) |
| 95 | |
| 96 | #define USBPHY_STATUS_RESUME_STATUS (1 << 10) |
| 97 | #define USBPHY_STATUS_OTGID_STATUS (1 << 8) |
| 98 | #define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) |
| 99 | #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) |
| 100 | |
| 101 | #define USBPHY_DEBUG_CLKGATE (1 << 30) |
| 102 | #define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) |
| 103 | #define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 |
| 104 | #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) |
| 105 | #define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) |
| 106 | #define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 |
| 107 | #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) |
| 108 | #define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) |
| 109 | #define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 |
| 110 | #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) |
| 111 | #define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 |
| 112 | #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) |
| 113 | #define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 |
| 114 | #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) |
| 115 | #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) |
| 116 | #define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) |
| 117 | |
| 118 | #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 |
| 119 | #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) |
| 120 | #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 |
| 121 | #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) |
| 122 | #define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 |
| 123 | #define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff |
| 124 | |
| 125 | #define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 |
| 126 | #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) |
| 127 | #define USBPHY_DEBUG1_ENTX2TX (1 << 12) |
| 128 | #define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 |
| 129 | #define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf |
| 130 | |
| 131 | #define USBPHY_VERSION_MAJOR_MASK (0xff << 24) |
| 132 | #define USBPHY_VERSION_MAJOR_OFFSET 24 |
| 133 | #define USBPHY_VERSION_MINOR_MASK (0xff << 16) |
| 134 | #define USBPHY_VERSION_MINOR_OFFSET 16 |
| 135 | #define USBPHY_VERSION_STEP_MASK 0xffff |
| 136 | #define USBPHY_VERSION_STEP_OFFSET 0 |
| 137 | |
| 138 | #define USBPHY_IP_DIV_SEL_OFFSET 23 |
| 139 | #define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) |
| 140 | #define USBPHY_IP_LFR_SEL_OFFSET 21 |
| 141 | #define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) |
| 142 | #define USBPHY_IP_CP_SEL_OFFSET 19 |
| 143 | #define USBPHY_IP_CP_SEL_MASK (0x3 << 19) |
| 144 | #define USBPHY_IP_TSTI_TX_DP (1 << 18) |
| 145 | #define USBPHY_IP_TSTI_TX_DM (1 << 17) |
| 146 | #define USBPHY_IP_ANALOG_TESTMODE (1 << 16) |
| 147 | #define USBPHY_IP_EN_USB_CLKS (1 << 2) |
| 148 | #define USBPHY_IP_PLL_LOCKED (1 << 1) |
| 149 | #define USBPHY_IP_PLL_POWER (1 << 0) |
| 150 | |
| 151 | #endif /* __REGS_USBPHY_H__ */ |