Blame - arch/arm/include/asm/fsl_secure_boot.h - filogic/uboot

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gaurav rana	f79323c	2015-03-10 14:08:50 +0530	[diff] [blame]	1	/*
				2	* Copyright 2015 Freescale Semiconductor, Inc.
				3	*
				4	* SPDX-License-Identifier: GPL-2.0+
				5	*/
				6
				7	#ifndef __FSL_SECURE_BOOT_H
				8	#define __FSL_SECURE_BOOT_H
				9
				10	#ifdef CONFIG_SECURE_BOOT
Aneesh Bansal	4310470	2016-01-22 16:37:24 +0530	[diff] [blame]	11
				12	#ifndef CONFIG_FIT_SIGNATURE
				13	#define CONFIG_CHAIN_OF_TRUST
				14	#endif
				15
				16	#endif
				17
				18	#ifdef CONFIG_CHAIN_OF_TRUST
Aneesh Bansal	d31bb3e	2015-07-31 14:10:03 +0530	[diff] [blame]	19	#define CONFIG_CMD_ESBC_VALIDATE
Aneesh Bansal	3322e21	2016-01-22 16:37:23 +0530	[diff] [blame]	20	#define CONFIG_CMD_BLOB
Saksham Jain	c0c38d2	2016-03-23 16:24:35 +0530	[diff] [blame]	21	#define CONFIG_CMD_HASH
Aneesh Bansal	d31bb3e	2015-07-31 14:10:03 +0530	[diff] [blame]	22	#define CONFIG_FSL_SEC_MON
Saksham Jain	c0c38d2	2016-03-23 16:24:35 +0530	[diff] [blame]	23	#define CONFIG_SHA_HW_ACCEL
Aneesh Bansal	d31bb3e	2015-07-31 14:10:03 +0530	[diff] [blame]	24	#define CONFIG_SHA_PROG_HW_ACCEL
Aneesh Bansal	d31bb3e	2015-07-31 14:10:03 +0530	[diff] [blame]	25	#define CONFIG_RSA_FREESCALE_EXP
Aneesh Bansal	b3e9820	2015-12-08 13:54:29 +0530	[diff] [blame]	26
Aneesh Bansal	d31bb3e	2015-07-31 14:10:03 +0530	[diff] [blame]	27	#ifndef CONFIG_FSL_CAAM
				28	#define CONFIG_FSL_CAAM
				29	#endif
				30
				31	#define CONFIG_KEY_REVOCATION
				32	#ifndef CONFIG_SYS_RAMBOOT
				33	/* The key used for verification of next level images
				34	* is picked up from an Extension Table which has
				35	* been verified by the ISBC (Internal Secure boot Code)
				36	* in boot ROM of the SoC.
				37	* The feature is only applicable in case of NOR boot and is
				38	* not applicable in case of RAMBOOT (NAND, SD, SPI).
				39	*/
Saksham Jain	6121f08	2016-03-23 16:24:34 +0530	[diff] [blame]	40	#ifndef CONFIG_ESBC_HDR_LS
				41	/* Current Key EXT feature not available in LS ESBC Header */
Aneesh Bansal	d31bb3e	2015-07-31 14:10:03 +0530	[diff] [blame]	42	#define CONFIG_FSL_ISBC_KEY_EXT
				43	#endif
				44
Saksham Jain	6121f08	2016-03-23 16:24:34 +0530	[diff] [blame]	45	#endif
				46
York Sun	cbe8e1c	2016-04-04 11:41:26 -0700	[diff] [blame]	47	#if defined(CONFIG_LS1043A) \|\| defined(CONFIG_LS2080A)
Saksham Jain	c0c38d2	2016-03-23 16:24:35 +0530	[diff] [blame]	48	/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
York Sun	cbe8e1c	2016-04-04 11:41:26 -0700	[diff] [blame]	49	* Similiarly for LS2080
Saksham Jain	c0c38d2	2016-03-23 16:24:35 +0530	[diff] [blame]	50	*/
Aneesh Bansal	962021a	2016-01-22 16:37:22 +0530	[diff] [blame]	51	#define CONFIG_ESBC_ADDR_64BIT
				52	#endif
				53
York Sun	cbe8e1c	2016-04-04 11:41:26 -0700	[diff] [blame]	54	#ifdef CONFIG_LS2080A
Saksham Jain	f0eb2ca	2016-03-23 16:24:38 +0530	[diff] [blame]	55	#define CONFIG_EXTRA_ENV \
				56	"setenv fdt_high 0xa0000000;" \
				57	"setenv initrd_high 0xcfffffff;" \
				58	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
				59	#else
gaurav rana	f79323c	2015-03-10 14:08:50 +0530	[diff] [blame]	60	#define CONFIG_EXTRA_ENV \
				61	"setenv fdt_high 0xcfffffff;" \
				62	"setenv initrd_high 0xcfffffff;" \
				63	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
Saksham Jain	f0eb2ca	2016-03-23 16:24:38 +0530	[diff] [blame]	64	#endif
gaurav rana	f79323c	2015-03-10 14:08:50 +0530	[diff] [blame]	65
Saksham Jain	503eab9	2016-03-23 16:24:37 +0530	[diff] [blame]	66	/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
				67	* Non-XIP Memory (Nand/SD)*/
York Sun	cbe8e1c	2016-04-04 11:41:26 -0700	[diff] [blame]	68	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_LS2080A)
Saksham Jain	503eab9	2016-03-23 16:24:37 +0530	[diff] [blame]	69	#define CONFIG_BOOTSCRIPT_COPY_RAM
				70	#endif
				71	/* The address needs to be modified according to NOR and DDR memory map */
York Sun	cbe8e1c	2016-04-04 11:41:26 -0700	[diff] [blame]	72	#ifdef CONFIG_LS2080A
Saksham Jain	503eab9	2016-03-23 16:24:37 +0530	[diff] [blame]	73	#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
				74	#define CONFIG_BS_ADDR_FLASH 0x583900000
				75	#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
				76	#define CONFIG_BS_ADDR_RAM 0xa3900000
				77	#else
				78	#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
				79	#define CONFIG_BS_ADDR_FLASH 0x60060000
				80	#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
				81	#define CONFIG_BS_ADDR_RAM 0xa0060000
				82	#endif
				83
				84	#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
				85	#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
				86	#define CONFIG_BS_HDR_SIZE 0x00002000
				87	#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
				88	#define CONFIG_BS_SIZE 0x00001000
Saksham Jain	506c2eb	2016-03-23 16:24:36 +0530	[diff] [blame]	89	#else
Saksham Jain	503eab9	2016-03-23 16:24:37 +0530	[diff] [blame]	90	#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH
				91	/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
Saksham Jain	506c2eb	2016-03-23 16:24:36 +0530	[diff] [blame]	92	#endif
gaurav rana	f79323c	2015-03-10 14:08:50 +0530	[diff] [blame]	93
Aneesh Bansal	4310470	2016-01-22 16:37:24 +0530	[diff] [blame]	94	#include <config_fsl_chain_trust.h>
				95	#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
gaurav rana	f79323c	2015-03-10 14:08:50 +0530	[diff] [blame]	96	#endif