| Tom Warren | f80dd82 | 2015-02-02 13:22:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010-2015 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TEGRA210_FLOW_H_ |
| 9 | #define _TEGRA210_FLOW_H_ |
| 10 | |
| 11 | struct flow_ctlr { |
| 12 | u32 halt_cpu_events; /* offset 0x00 */ |
| 13 | u32 halt_cop_events; /* offset 0x04 */ |
| 14 | u32 cpu_csr; /* offset 0x08 */ |
| 15 | u32 cop_csr; /* offset 0x0c */ |
| 16 | u32 xrq_events; /* offset 0x10 */ |
| 17 | u32 halt_cpu1_events; /* offset 0x14 */ |
| 18 | u32 cpu1_csr; /* offset 0x18 */ |
| 19 | u32 halt_cpu2_events; /* offset 0x1c */ |
| 20 | u32 cpu2_csr; /* offset 0x20 */ |
| 21 | u32 halt_cpu3_events; /* offset 0x24 */ |
| 22 | u32 cpu3_csr; /* offset 0x28 */ |
| 23 | u32 cluster_control; /* offset 0x2c */ |
| 24 | u32 halt_cop1_events; /* offset 0x30 */ |
| 25 | u32 halt_cop1_csr; /* offset 0x34 */ |
| 26 | u32 cpu_pwr_csr; /* offset 0x38 */ |
| 27 | u32 mpid; /* offset 0x3c */ |
| 28 | u32 ram_repair; /* offset 0x40 */ |
| 29 | }; |
| 30 | |
| 31 | /* HALT_COP_EVENTS_0, 0x04 */ |
| 32 | #define EVENT_MSEC (1 << 24) |
| 33 | #define EVENT_USEC (1 << 25) |
| 34 | #define EVENT_JTAG (1 << 28) |
| 35 | #define EVENT_MODE_STOP (2 << 29) |
| 36 | |
| 37 | /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ |
| 38 | #define ACTIVE_LP (1 << 0) |
| 39 | |
| 40 | /* CPUn_CSR_0 */ |
| 41 | #define CSR_ENABLE (1 << 0) |
| 42 | #define CSR_IMMEDIATE_WAKE (1 << 3) |
| 43 | #define CSR_WAIT_WFI_SHIFT 8 |
| 44 | |
| 45 | #endif /* _TEGRA210_FLOW_H_ */ |