| Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2016 |
| 3 | * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef _ASM_ARCH_HARDWARE_H |
| 9 | #define _ASM_ARCH_HARDWARE_H |
| 10 | |
| 11 | /* STM32F746 */ |
| 12 | #define ITCM_FLASH_BASE 0x00200000UL |
| 13 | #define AXIM_FLASH_BASE 0x08000000UL |
| 14 | |
| 15 | #define ITCM_SRAM_BASE 0x00000000UL |
| 16 | #define DTCM_SRAM_BASE 0x20000000UL |
| 17 | #define SRAM1_BASE 0x20010000UL |
| 18 | #define SRAM2_BASE 0x2004C000UL |
| 19 | |
| 20 | #define PERIPH_BASE 0x40000000UL |
| 21 | |
| 22 | #define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) |
| 23 | #define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000) |
| 24 | #define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000) |
| 25 | #define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000) |
| 26 | #define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000) |
| 27 | |
| 28 | #define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) |
| 29 | #define USART2_BASE (APB1_PERIPH_BASE + 0x4400) |
| 30 | #define USART3_BASE (APB1_PERIPH_BASE + 0x4800) |
| 31 | #define PWR_BASE (APB1_PERIPH_BASE + 0x7000) |
| 32 | |
| 33 | #define USART1_BASE (APB2_PERIPH_BASE + 0x1000) |
| 34 | #define USART6_BASE (APB2_PERIPH_BASE + 0x1400) |
| 35 | |
| 36 | #define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) |
| 37 | #define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) |
| 38 | #define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800) |
| 39 | #define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00) |
| 40 | #define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000) |
| 41 | #define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400) |
| 42 | #define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800) |
| 43 | #define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00) |
| 44 | #define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000) |
| 45 | #define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400) |
| 46 | #define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800) |
| 47 | #define RCC_BASE (AHB1_PERIPH_BASE + 0x3800) |
| 48 | #define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00) |
| 49 | |
| 50 | |
| 51 | #define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140) |
| 52 | |
| Vikas Manocha | 4940802 | 2016-03-09 15:18:14 -0800 | [diff] [blame] | 53 | static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { |
| 54 | [0 ... 3] = 32 * 1024, |
| 55 | [4] = 128 * 1024, |
| 56 | [5 ... 7] = 256 * 1024 |
| 57 | }; |
| 58 | |
| Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 59 | enum clock { |
| 60 | CLOCK_CORE, |
| 61 | CLOCK_AHB, |
| 62 | CLOCK_APB1, |
| 63 | CLOCK_APB2 |
| 64 | }; |
| 65 | #define STM32_BUS_MASK 0xFFFF0000 |
| 66 | |
| 67 | int configure_clocks(void); |
| 68 | |
| 69 | #endif /* _ASM_ARCH_HARDWARE_H */ |