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git01.mediatek.com / filogic / uboot / 388ef184770941e596aef41d281d0c5d15c0a46f / . / arch / arm / dts / imx8qm-rom7720-a1.dts
blob: 332d441c6d3336f3fc6092ccd90a300dfc421ca2 [file] [log] [blame]
Oliver Grautedafcd992019-09-20 07:08:41 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
5 */
6
7/dts-v1/;
8
9/* First 128KB is for PSCI ATF. */
10/memreserve/ 0x80000000 0x00020000;
11
12#include "fsl-imx8qm.dtsi"
Oliver Graute3e0bf762022-11-04 16:03:37 +0100[diff] [blame]13#include "imx8qm-u-boot.dtsi"
Oliver Grautedafcd992019-09-20 07:08:41 +0000[diff] [blame]14
15/ {
16 model = "Advantech iMX8QM Qseven series";
17 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
18
19 chosen {
20 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
21 stdout-path = &lpuart0;
22 };
23
24 leds {
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_leds>;
28 user {
29 label = "heartbeat";
30 gpios = <&gpio2 15 0>;
31 default-state = "on";
32 linux,default-trigger = "heartbeat";
33 };
34 };
35
36 regulators {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 reg_usb_otg1_vbus: regulator@0 {
42 compatible = "regulator-fixed";
43 reg = <0>;
44 regulator-name = "usb_otg1_vbus";
45 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>;
47 gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
48 enable-active-high;
49 };
50
51 reg_usdhc2_vmmc: usdhc2_vmmc {
52 compatible = "regulator-fixed";
53 regulator-name = "sw-3p3-sd1";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
57 enable-active-high;
58 };
59 };
60};
61
62&iomuxc {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_hog_1>;
65
66 imx8qm-mek {
67 pinctrl_hog_1: hoggrp-1 {
68 fsl,pins = <
69 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
70 >;
71 };
72
73 pinctrl_fec1: fec1grp {
74 fsl,pins = <
75 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
76 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
77 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
78 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
79 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
80 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
81 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
82 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
83 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
84 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
85 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
86 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
87 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
88 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
89 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
90 >;
91 };
92
93 pinctrl_fec2: fec2grp {
94 fsl,pins = <
95 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
96 SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
97 SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
98 SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
99 SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
100 SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
101 SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
102 SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
103 SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
104 SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
105 SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
106 SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
107 SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
108 >;
109 };
110
111 pinctrl_lpuart0: lpuart0grp {
112 fsl,pins = <
113 SC_P_UART0_RX_DMA_UART0_RX 0x06000020
114 SC_P_UART0_TX_DMA_UART0_TX 0x06000020
115 >;
116 };
117
118 pinctrl_usdhc1: usdhc1grp {
119 fsl,pins = <
120 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
121 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
122 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
123 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
124 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
125 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
126 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
127 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
128 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
129 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
130 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
131 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
132 >;
133 };
134
135 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
136 fsl,pins = <
137 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
138 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
139 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
140 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
141 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
142 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
143 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
144 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
145 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
146 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
147 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
148 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
149 >;
150 };
151
152 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
153 fsl,pins = <
154 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
155 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
156 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
157 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
158 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
159 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
160 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
161 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
162 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
163 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
164 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
165 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
166 >;
167 };
168
169 pinctrl_usdhc2_gpio: usdhc2grpgpio {
170 fsl,pins = <
171 SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
172 SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
173 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
174 >;
175 };
176
177 pinctrl_usdhc2: usdhc2grp {
178 fsl,pins = <
179 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
180 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
181 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
182 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
183 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
184 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
185 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
186 >;
187 };
188
189 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
190 fsl,pins = <
191 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
192 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
193 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
194 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
195 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
196 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
197 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
198 >;
199 };
200
201 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
202 fsl,pins = <
203 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
204 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
205 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
206 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
207 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
208 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
209 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
210 >;
211 };
212
213 pinctrl_usdhc3: usdhc3grp {
214 fsl,pins = <
215 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
216 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
217 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
218 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
219 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
220 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
221 /* WP */
222 SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
223 /* CD */
224 SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
225 >;
226 };
227
228 pinctrl_lpi2c1: lpi2c1grp {
229 fsl,pins = <
230 SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020
231 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020
232 /*
233 * Change the default alt function from SCL/SDA to others,
234 * to avoid select input conflict with GPT0
235 */
236 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c
237 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c
238 SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c
239 SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c
240 >;
241 };
242
243 pinctrl_gpio_leds: gpioledsgrp {
244 fsl,pins = <
245 SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
246 >;
247 };
248 };
249};
250
251&gpio2 {
252 status = "okay";
253};
254
255&gpio4 {
256 status = "okay";
257};
258
259&gpio5 {
260 status = "okay";
261};
262
263&usdhc1 {
264 pinctrl-names = "default", "state_100mhz", "state_200mhz";
265 pinctrl-0 = <&pinctrl_usdhc1>;
266 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
267 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
268 bus-width = <8>;
269 non-removable;
270 status = "okay";
271};
272
273&usdhc2 {
274 pinctrl-names = "default", "state_100mhz", "state_200mhz";
275 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
276 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
277 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
278 bus-width = <4>;
279 cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
280 wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
281 vmmc-supply = <&reg_usdhc2_vmmc>;
282 status = "okay";
283};
284
285&usdhc3 {
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_usdhc3>;
288 bus-width = <4>;
289 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
290 wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
291 status = "okay";
292};
293
294&fec1 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_fec1>;
Oliver Graute30c3b622020-12-04 15:26:16 +0100[diff] [blame]297 phy-mode = "rgmii-id";
Oliver Grautedafcd992019-09-20 07:08:41 +0000[diff] [blame]298 phy-handle = <&ethphy0>;
299 fsl,ar8031-phy-fixup;
300 fsl,magic-packet;
301 status = "okay";
302
303 mdio {
304 #address-cells = <1>;
305 #size-cells = <0>;
306
307 ethphy0: ethernet-phy@0 {
308 compatible = "ethernet-phy-ieee802.3-c22";
309 reg = <0>;
310 };
311
312 ethphy1: ethernet-phy@1 {
313 compatible = "ethernet-phy-ieee802.3-c22";
314 reg = <1>;
315 };
316 };
317};
318
319&fec2 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_fec2>;
Oliver Graute30c3b622020-12-04 15:26:16 +0100[diff] [blame]322 phy-mode = "rgmii-id";
Oliver Grautedafcd992019-09-20 07:08:41 +0000[diff] [blame]323 phy-handle = <&ethphy1>;
324 fsl,ar8031-phy-fixup;
325 fsl,magic-packet;
326 status = "okay";
327};
328
329&i2c1 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 clock-frequency = <100000>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_lpi2c1>;
335 status = "okay";
336
337 pca9557_a: gpio@18 {
338 compatible = "nxp,pca9557";
339 reg = <0x18>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 };
343
344 pca9557_b: gpio@19 {
345 compatible = "nxp,pca9557";
346 reg = <0x19>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 };
350
351 pca9557_c: gpio@1b {
352 compatible = "nxp,pca9557";
353 reg = <0x1b>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 };
357
358 pca9557_d: gpio@1f {
359 compatible = "nxp,pca9557";
360 reg = <0x1f>;
361 gpio-controller;
362 #gpio-cells = <2>;
363 };
364};
365
366&lpuart0 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_lpuart0>;
369 status = "okay";
370};
371
372&lpuart1 {
373 status = "okay";
374};