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git01.mediatek.com / filogic / uboot / 388ef184770941e596aef41d281d0c5d15c0a46f / . / arch / arm / dts / imx8mm-phg-u-boot.dtsi
blob: c9e0b4420500f94633b811bc15801152951d25fb [file] [log] [blame]
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]13 };
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]14};
15
16&aips4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]18};
19
20&reg_usdhc2_vmmc {
21 u-boot,off-on-delay-us = <20000>;
22};
23
24&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]26};
27
28&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]30};
31
32&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]34};
35
36&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]38};
39
40&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]42};
43
44&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]46};
47
48&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]50};
51
52&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]54};
55
56&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]58};
59
60&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]62};
63
64&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]66};
67
68&usbmisc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]70};
71
72&usbphynop1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]74};
75
76&usbotg1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]78};
79
80&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]82};
83
84&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]86 sd-uhs-sdr104;
87 sd-uhs-ddr50;
88 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
89 assigned-clock-rates = <400000000>;
90 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
91};
92
93&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]95 mmc-hs400-1_8v;
96 mmc-hs400-enhanced-strobe;
97 /*
98 * prevents voltage switch warn: driver will switch even at
99 * fixed voltage
100 */
101 /delete-property/ vmmc-supply;
102 /delete-property/ vqmmc-supply;
103 assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
104 assigned-clock-rates = <400000000>;
105 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
106};
107
108&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]110};
111
112&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]114};
115
116&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]118};
119
120&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]122};
123
124&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]126};
127
128&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]130};