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git01.mediatek.com / filogic / uboot / 3869f2d54a835e509a55c47a9c4331bcc33a53d0 / . / arch / arm / dts / imx8mp-evk-u-boot.dtsi
blob: 6d9b229989ac0176fc7544d5a7cbac51eb90cc87 [file] [log] [blame]
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]4 */
5
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]6#include "imx8mp-u-boot.dtsi"
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]7
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]8/ {
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]13 };
14};
15
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]16&reg_usdhc2_vmmc {
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]17 u-boot,off-on-delay-us = <20000>;
18};
19
20&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]22};
23
24&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]26};
27
28&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]30};
31
32&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]34};
35
36&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]38};
39
Peng Fane22df442022-05-05 19:05:59 +0800[diff] [blame]40&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Peng Fane22df442022-05-05 19:05:59 +0800[diff] [blame]42};
43
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]44&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]46};
47
48&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]50};
51
52&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]54};
55
56&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]58};
59
60&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]62};
63
64&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]66};
67
68&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]70};
71
72&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]74};
75
76&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]78};
79
80&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]82};
83
84&i2c5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]86};
87
88&i2c6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]90};
91
92&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]94};
95
96&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]98 sd-uhs-sdr104;
99 sd-uhs-ddr50;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]100};
101
102&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]104 mmc-hs400-1_8v;
105 mmc-hs400-enhanced-strobe;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]106};
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]107
108&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]110};
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]111
Ye Li25804942021-08-16 18:44:28 +0800[diff] [blame]112&ethphy0 {
113 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
114 reset-delay-us = <15000>;
115 reset-post-delay-us = <100000>;
116};
117
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]118&fec {
119 phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
Ye Lid1b82062021-02-18 22:33:48 -0800[diff] [blame]120 phy-reset-duration = <15>;
121 phy-reset-post-delay = <100>;
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]122};
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]123
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]124