| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Rafal Jaworowski | 86a28e9 | 2008-01-15 12:52:31 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> |
| 4 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> |
| 5 | * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> |
| Kumar Gala | 6a6d948 | 2009-07-28 21:49:52 -0500 | [diff] [blame] | 6 | * Copyright Freescale Semiconductor, Inc. 2004, 2006. |
| Rafal Jaworowski | 86a28e9 | 2008-01-15 12:52:31 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <config.h> |
| 10 | #include <ppc_asm.tmpl> |
| Valentin Longchamp | b8cb075 | 2015-03-27 16:07:32 +0100 | [diff] [blame] | 11 | #include <ppc_defs.h> |
| 12 | |
| 13 | #include <asm/cache.h> |
| Rafal Jaworowski | 86a28e9 | 2008-01-15 12:52:31 +0100 | [diff] [blame] | 14 | |
| 15 | /*------------------------------------------------------------------------------- */ |
| 16 | /* Function: ppcDcbf */ |
| 17 | /* Description: Data Cache block flush */ |
| 18 | /* Input: r3 = effective address */ |
| 19 | /* Output: none. */ |
| 20 | /*------------------------------------------------------------------------------- */ |
| 21 | .globl ppcDcbf |
| 22 | ppcDcbf: |
| 23 | dcbf r0,r3 |
| 24 | blr |
| 25 | |
| 26 | /*------------------------------------------------------------------------------- */ |
| 27 | /* Function: ppcDcbi */ |
| 28 | /* Description: Data Cache block Invalidate */ |
| 29 | /* Input: r3 = effective address */ |
| 30 | /* Output: none. */ |
| 31 | /*------------------------------------------------------------------------------- */ |
| 32 | .globl ppcDcbi |
| 33 | ppcDcbi: |
| 34 | dcbi r0,r3 |
| 35 | blr |
| 36 | |
| 37 | /*-------------------------------------------------------------------------- |
| 38 | * Function: ppcDcbz |
| 39 | * Description: Data Cache block zero. |
| 40 | * Input: r3 = effective address |
| 41 | * Output: none. |
| 42 | *-------------------------------------------------------------------------- */ |
| 43 | |
| 44 | .globl ppcDcbz |
| 45 | ppcDcbz: |
| 46 | dcbz r0,r3 |
| 47 | blr |
| 48 | |
| 49 | /*------------------------------------------------------------------------------- */ |
| 50 | /* Function: ppcSync */ |
| 51 | /* Description: Processor Synchronize */ |
| 52 | /* Input: none. */ |
| 53 | /* Output: none. */ |
| 54 | /*------------------------------------------------------------------------------- */ |
| 55 | .globl ppcSync |
| 56 | ppcSync: |
| 57 | sync |
| 58 | blr |
| Valentin Longchamp | b8cb075 | 2015-03-27 16:07:32 +0100 | [diff] [blame] | 59 | |
| 60 | /* |
| 61 | * Write any modified data cache blocks out to memory and invalidate them. |
| 62 | * Does not invalidate the corresponding instruction cache blocks. |
| 63 | * |
| 64 | * flush_dcache_range(unsigned long start, unsigned long stop) |
| 65 | */ |
| 66 | _GLOBAL(flush_dcache_range) |
| Heiko Schocher | 2028012 | 2017-06-27 16:49:14 +0200 | [diff] [blame] | 67 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
| Valentin Longchamp | b8cb075 | 2015-03-27 16:07:32 +0100 | [diff] [blame] | 68 | li r5,L1_CACHE_BYTES-1 |
| 69 | andc r3,r3,r5 |
| 70 | subf r4,r3,r4 |
| 71 | add r4,r4,r5 |
| 72 | srwi. r4,r4,L1_CACHE_SHIFT |
| 73 | beqlr |
| 74 | mtctr r4 |
| 75 | |
| 76 | 1: dcbf 0,r3 |
| 77 | addi r3,r3,L1_CACHE_BYTES |
| 78 | bdnz 1b |
| 79 | sync /* wait for dcbst's to get to ram */ |
| York Sun | d0bb57b | 2016-04-07 09:56:48 -0700 | [diff] [blame] | 80 | #endif |
| Valentin Longchamp | b8cb075 | 2015-03-27 16:07:32 +0100 | [diff] [blame] | 81 | blr |
| 82 | |
| 83 | /* |
| 84 | * Like above, but invalidate the D-cache. This is used by the 8xx |
| 85 | * to invalidate the cache so the PPC core doesn't get stale data |
| 86 | * from the CPM (no cache snooping here :-). |
| 87 | * |
| 88 | * invalidate_dcache_range(unsigned long start, unsigned long stop) |
| 89 | */ |
| 90 | _GLOBAL(invalidate_dcache_range) |
| Heiko Schocher | 2028012 | 2017-06-27 16:49:14 +0200 | [diff] [blame] | 91 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
| Valentin Longchamp | b8cb075 | 2015-03-27 16:07:32 +0100 | [diff] [blame] | 92 | li r5,L1_CACHE_BYTES-1 |
| 93 | andc r3,r3,r5 |
| 94 | subf r4,r3,r4 |
| 95 | add r4,r4,r5 |
| 96 | srwi. r4,r4,L1_CACHE_SHIFT |
| 97 | beqlr |
| 98 | mtctr r4 |
| 99 | |
| 100 | sync |
| 101 | 1: dcbi 0,r3 |
| 102 | addi r3,r3,L1_CACHE_BYTES |
| 103 | bdnz 1b |
| 104 | sync /* wait for dcbi's to get to ram */ |
| York Sun | d0bb57b | 2016-04-07 09:56:48 -0700 | [diff] [blame] | 105 | #endif |
| Valentin Longchamp | b8cb075 | 2015-03-27 16:07:32 +0100 | [diff] [blame] | 106 | blr |
| 107 | |