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git01.mediatek.com / filogic / uboot / 3854a1a84f87b6d0a56687105dbdb7ae9b2bf690 / . / configs / chromebit_mickey_defconfig
blob: b4d017c6a4da5826a1f8ef68e83c25faec28f0aa [file] [log] [blame]
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00100000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]4CONFIG_SYS_MALLOC_F_LEN=0x2000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]5CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]6# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]7CONFIG_TARGET_CHROMEBIT_MICKEY=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]8CONFIG_DEBUG_UART_BASE=0xff690000
9CONFIG_DEBUG_UART_CLOCK=24000000
10CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]11CONFIG_SPL_SPI_FLASH_SUPPORT=y
12CONFIG_SPL_SPI_SUPPORT=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]13CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]14CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]15# CONFIG_ANDROID_BOOT_IMAGE is not set
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]16CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]17# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]18CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]19CONFIG_SPL_STACK_R=y
20CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]21CONFIG_SPL_SPI_LOAD=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]22CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]23CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]24CONFIG_CMD_I2C=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]25CONFIG_CMD_MMC=y
26CONFIG_CMD_SF=y
Simon Glass86b1b652017-08-04 16:34:46 -0600[diff] [blame]27CONFIG_CMD_SF_TEST=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]28CONFIG_CMD_SPI=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]29CONFIG_CMD_USB=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]30# CONFIG_CMD_SETEXPR is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]31CONFIG_CMD_CACHE=y
32CONFIG_CMD_TIME=y
33CONFIG_CMD_PMIC=y
34CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]35# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]36# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]37CONFIG_SPL_PARTITION_UUIDS=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]38CONFIG_SPL_OF_CONTROL=y
39CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]40CONFIG_SPL_OF_PLATDATA=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]41CONFIG_REGMAP=y
42CONFIG_SPL_REGMAP=y
43CONFIG_SYSCON=y
44CONFIG_SPL_SYSCON=y
45# CONFIG_SPL_SIMPLE_BUS is not set
46CONFIG_CLK=y
47CONFIG_SPL_CLK=y
Alex Kiernane80d2942018-05-29 15:30:55 +0000[diff] [blame]48CONFIG_FASTBOOT_FLASH=y
49CONFIG_FASTBOOT_FLASH_MMC_DEV=0
50CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]51CONFIG_ROCKCHIP_GPIO=y
52CONFIG_I2C_CROS_EC_TUNNEL=y
53CONFIG_SYS_I2C_ROCKCHIP=y
54CONFIG_I2C_MUX=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]55CONFIG_DM_KEYBOARD=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]56CONFIG_CROS_EC_KEYB=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]57CONFIG_CROS_EC=y
58CONFIG_CROS_EC_SPI=y
59CONFIG_PWRSEQ=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]60CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]61CONFIG_MMC_DW_ROCKCHIP=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]62CONFIG_PINCTRL=y
63CONFIG_SPL_PINCTRL=y
64# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]65CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]66CONFIG_DM_PMIC=y
67# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]68CONFIG_PMIC_RK8XX=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]69CONFIG_SPL_DM_REGULATOR=y
70CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]71CONFIG_REGULATOR_RK8XX=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]72CONFIG_PWM_ROCKCHIP=y
73CONFIG_RAM=y
74CONFIG_SPL_RAM=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]75CONFIG_DEBUG_UART_SHIFT=2
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]76CONFIG_ROCKCHIP_SERIAL=y
77CONFIG_ROCKCHIP_SPI=y
78CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]79CONFIG_USB=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]80CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini6c3798f2018-02-10 20:27:45 -0500[diff] [blame]81CONFIG_USB_STORAGE=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]82CONFIG_USB_GADGET=y
Maxime Ripard7f78b9d2017-09-07 08:58:08 +0200[diff] [blame]83CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
84CONFIG_USB_GADGET_VENDOR_NUM=0x2207
85CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]86CONFIG_USB_GADGET_DWC2_OTG=y
Lukasz Majewskie364e4b2018-01-29 19:25:54 +0100[diff] [blame]87CONFIG_USB_FUNCTION_MASS_STORAGE=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]88CONFIG_DM_VIDEO=y
89CONFIG_DISPLAY=y
90CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]91CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]92CONFIG_USE_TINY_PRINTF=y
93CONFIG_CMD_DHRYSTONE=y
94CONFIG_ERRNO_STR=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]95# CONFIG_SPL_OF_LIBFDT is not set