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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +09002/*
3 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4 * Copyright (C) 2012 Renesas Solutions Corp.
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +09005 */
6
7#ifndef __KZM9G_H
8#define __KZM9G_H
9
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090010#define CONFIG_SH73A0
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090011#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
12
13#include <asm/arch/rmobile.h>
14
15#define CONFIG_ARCH_CPU_INIT
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090016
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090017#define CONFIG_CMDLINE_TAG
18#define CONFIG_SETUP_MEMORY_TAGS
19#define CONFIG_INITRD_TAG
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090020
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090021/* MEMORY */
22#define KZM_SDRAM_BASE (0x40000000)
23#define PHYS_SDRAM KZM_SDRAM_BASE
24#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090025
26/* NOR Flash */
27#define KZM_FLASH_BASE (0x00000000)
28#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
29#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
30#define CONFIG_SYS_MAX_FLASH_BANKS (1)
31#define CONFIG_SYS_MAX_FLASH_SECT (512)
32
33/* prompt */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090034#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090035#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
36
37/* SCIF */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090038#define CONFIG_CONS_SCIF4
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090039
40#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
41#define CONFIG_SYS_MEMTEST_END \
42 (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090043#undef CONFIG_SYS_MEMTEST_SCRATCH
44#undef CONFIG_SYS_LOADS_BAUD_CHANGE
45
46#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
47#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
48#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
49#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
50 CONFIG_SYS_INIT_RAM_SIZE - \
51 GENERATED_GBL_DATA_SIZE)
Tetsuyuki Kobayashi6a8c5152012-07-05 01:43:44 +000052#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
53#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
54#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090055#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
56
57#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
58#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090059#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
60
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090061#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
62
63/* FLASH */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090064#undef CONFIG_SYS_FLASH_QUIET_TEST
65#define CONFIG_SYS_FLASH_EMPTY_INFO
66#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
67#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
68#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
69#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
70
71/* Timeout for Flash erase operations (in ms) */
72#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
73/* Timeout for Flash write operations (in ms) */
74#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
75/* Timeout for Flash set sector lock bit operations (in ms) */
76#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
77/* Timeout for Flash clear lock bit operations (in ms) */
78#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
79
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090080#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090081
82/* GPIO / PFC */
83#define CONFIG_SH_GPIO_PFC
84
85/* Clock */
Nobuhiro Iwamatsu8c002362012-08-03 13:56:52 +090086#define CONFIG_GLOBAL_TIMER
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090087#define CONFIG_SYS_CLK_FREQ (48000000)
88#define CONFIG_SYS_CPU_CLK (1196000000)
Nobuhiro Iwamatsuadbaef52013-09-30 10:30:40 +090089#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090090#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090091
Tetsuyuki Kobayashi3d743272012-07-25 18:24:18 +000092#define CONFIG_NFS_TIMEOUT 10000UL
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090093
94/* I2C */
Nobuhiro Iwamatsu12240102013-10-29 13:33:51 +090095#define CONFIG_SYS_I2C
96#define CONFIG_SYS_I2C_SH
97#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
98#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
99#define CONFIG_SYS_I2C_SH_SPEED0 100000
100#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
101#define CONFIG_SYS_I2C_SH_SPEED1 100000
102#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
103#define CONFIG_SYS_I2C_SH_SPEED2 100000
104#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
105#define CONFIG_SYS_I2C_SH_SPEED3 100000
106#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
107#define CONFIG_SYS_I2C_SH_SPEED4 100000
Tetsuyuki Kobayashicc4283c2012-09-13 19:07:56 +0000108#define CONFIG_SH_I2C_8BIT
Nobuhiro Iwamatsu12240102013-10-29 13:33:51 +0900109#define CONFIG_SH_I2C_DATA_HIGH 4
110#define CONFIG_SH_I2C_DATA_LOW 5
111#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +0900112
113#endif /* __KZM9G_H */