blob: b175e9d5745da24c30b0cff0dfd7df5e250cfc0a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Phil Sutterd76eba62015-12-25 14:41:25 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Phil Sutterd76eba62015-12-25 14:41:25 +01004 */
5
6#ifndef _CONFIG_SYNOLOGY_DS414_H
7#define _CONFIG_SYNOLOGY_DS414_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Phil Sutterd76eba62015-12-25 14:41:25 +010012
13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Phil Sutterd76eba62015-12-25 14:41:25 +010018#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
20/*
21 * Commands configuration
22 */
Phil Sutterd76eba62015-12-25 14:41:25 +010023
24/* I2C */
25#define CONFIG_SYS_I2C
26#define CONFIG_SYS_I2C_MVTWSI
27#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
28#define CONFIG_SYS_I2C_SLAVE 0x0
29#define CONFIG_SYS_I2C_SPEED 100000
30
Phil Sutterd76eba62015-12-25 14:41:25 +010031/* Environment in SPI NOR flash */
Phil Sutterd76eba62015-12-25 14:41:25 +010032#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
33#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
34#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
35
Phil Sutterd76eba62015-12-25 14:41:25 +010036#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
37
Phil Sutterd76eba62015-12-25 14:41:25 +010038/* PCIe support */
39#ifndef CONFIG_SPL_BUILD
Phil Sutterd76eba62015-12-25 14:41:25 +010040#define CONFIG_PCI_SCAN_SHOW
41#endif
42
43/* USB/EHCI/XHCI configuration */
44
Phil Sutterd76eba62015-12-25 14:41:25 +010045#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
46
47/* FIXME: broken XHCI support
48 * Below defines should enable support for the two rear USB3 ports. Sadly, this
49 * does not work because:
50 * - xhci-pci seems to not support DM_USB, so with that enabled it is not
51 * found.
52 * - USB init fails, controller does not respond in time */
Phil Sutterd76eba62015-12-25 14:41:25 +010053
Masahiro Yamada58d00232016-06-04 07:35:03 +090054#if !defined(CONFIG_USB_XHCI_HCD)
Phil Sutterd76eba62015-12-25 14:41:25 +010055#define CONFIG_EHCI_IS_TDI
56#endif
57
58/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
Phil Sutterd76eba62015-12-25 14:41:25 +010059
60/*
61 * mv-common.h should be defined after CMD configs since it used them
62 * to enable certain macros
63 */
64#include "mv-common.h"
65
66/*
67 * Memory layout while starting into the bin_hdr via the
68 * BootROM:
69 *
70 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
71 * 0x4000.4030 bin_hdr start address
72 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
73 * 0x4007.fffc BootROM stack top
74 *
75 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
76 * L2 cache thus cannot be used.
77 */
78
79/* SPL */
80/* Defines for SPL */
Phil Sutterd76eba62015-12-25 14:41:25 +010081#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
82
83#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
84#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
85
86#ifdef CONFIG_SPL_BUILD
87#define CONFIG_SYS_MALLOC_SIMPLE
88#endif
89
90#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
91#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
92
Phil Sutterd76eba62015-12-25 14:41:25 +010093/* SPL related SPI defines */
Phil Sutterd76eba62015-12-25 14:41:25 +010094#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
95
96/* DS414 bus width is 32bits */
97#define CONFIG_DDR_32BIT
98
Phil Sutterd76eba62015-12-25 14:41:25 +010099/* Default Environment */
100#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
Phil Sutterd76eba62015-12-25 14:41:25 +0100101#define CONFIG_LOADADDR 0x80000
Phil Sutterd76eba62015-12-25 14:41:25 +0100102
103#endif /* _CONFIG_SYNOLOGY_DS414_H */