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git01.mediatek.com / filogic / uboot / 385309c72ed8d7043e5fd238df3f83d871f3398d / . / arch / powerpc / include / asm / global_data.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]2/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +0200[diff] [blame]3 * (C) Copyright 2002-2010
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]5 */
6
7#ifndef __ASM_GBL_DATA_H
8#define __ASM_GBL_DATA_H
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]9
Peter Tyserbe34d1d2009-09-21 11:20:37 -0500[diff] [blame]10#include "config.h"
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]11#include "asm/types.h"
12
Simon Glass3ac47d72012-12-13 20:48:30 +0000[diff] [blame]13/* Architecture-specific global data */
14struct arch_global_data {
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]15#if defined(CONFIG_FSL_ESDHC)
16 u32 sdhc_clk;
Yangbo Lub124f8a2015-04-22 13:57:00 +0800[diff] [blame]17#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
18 u8 sdhc_adapter;
19#endif
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]20#endif
Christophe Leroyb3510fb2018-03-16 17:20:41 +0100[diff] [blame]21#if defined(CONFIG_MPC8xx)
Christophe Leroy069fa832017-07-06 10:23:22 +0200[diff] [blame]22 unsigned long brg_clk;
23#endif
Simon Glass34a194f2012-12-13 20:48:44 +0000[diff] [blame]24#if defined(CONFIG_CPM2)
Simon Glass44ea8512012-12-13 20:48:46 +0000[diff] [blame]25 /* There are many clocks on the MPC8260 - see page 9-5 */
26 unsigned long vco_out;
27 unsigned long cpm_clk;
28 unsigned long scc_clk;
Simon Glass34a194f2012-12-13 20:48:44 +0000[diff] [blame]29 unsigned long brg_clk;
30#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]31 /* TODO: sjg@chromium.org: Should these be unslgned long? */
Peter Tyser62e73982009-05-22 17:23:24 -0500[diff] [blame]32#if defined(CONFIG_MPC83xx)
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]33#ifdef CONFIG_CLK_MPC83XX
34 u32 core_clk;
35#else
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]36 /* There are other clocks in the MPC83XX */
37 u32 csb_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]38# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]39 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]40 u32 tsec1_clk;
41 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]42 u32 usbdr_clk;
Mario Sixb2e701c2019-01-21 09:17:24 +0100[diff] [blame]43# elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000[diff] [blame]44 u32 usbdr_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]45# endif
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]46# if defined(CONFIG_ARCH_MPC834X)
Scott Woodbeb638a2007-04-16 14:34:18 -0500[diff] [blame]47 u32 usbmph_clk;
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]48# endif /* CONFIG_ARCH_MPC834X */
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]49# if defined(CONFIG_ARCH_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +0800[diff] [blame]50 u32 tdm_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]51# endif
Dave Liua46daea2006-11-03 19:33:44 -0600[diff] [blame]52 u32 core_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]53 u32 enc_clk;
54 u32 lbiu_clk;
55 u32 lclk_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]56# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]57 defined(CONFIG_ARCH_MPC837X)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]58 u32 pciexp1_clk;
59 u32 pciexp2_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]60# endif
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]61# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]62 u32 sata_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]63# endif
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]64# if defined(CONFIG_ARCH_MPC8360)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]65 u32 mem_sec_clk;
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]66# endif /* CONFIG_ARCH_MPC8360 */
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]67#endif
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]68#endif
Simon Glassa8b57392012-12-13 20:48:48 +0000[diff] [blame]69#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
70 u32 lbc_clk;
71 void *cpu;
72#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
Simon Glassc2baaec2012-12-13 20:48:49 +0000[diff] [blame]73#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
74 defined(CONFIG_MPC86xx)
75 u32 i2c1_clk;
76 u32 i2c2_clk;
77#endif
Simon Glass8518b172012-12-13 20:48:50 +0000[diff] [blame]78#if defined(CONFIG_QE)
79 u32 qe_clk;
80 u32 brg_clk;
81 uint mp_alloc_base;
82 uint mp_alloc_top;
83#endif /* CONFIG_QE */
Simon Glassc6622d62012-12-13 20:48:51 +0000[diff] [blame]84#if defined(CONFIG_FSL_LAW)
85 u32 used_laws;
86#endif
Simon Glass0b466582012-12-13 20:48:52 +0000[diff] [blame]87#if defined(CONFIG_E500)
88 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
89#endif
Simon Glass4d6eaa32012-12-13 20:48:56 +0000[diff] [blame]90 unsigned long reset_status; /* reset status register at boot */
Simon Glass387a1f22012-12-13 20:48:57 +0000[diff] [blame]91#if defined(CONFIG_MPC83xx)
92 unsigned long arbiter_event_attributes;
93 unsigned long arbiter_event_address;
94#endif
Simon Glass89370732017-01-23 13:31:23 -0700[diff] [blame]95#if defined(CONFIG_CPM2)
Simon Glass93980082012-12-13 20:48:58 +0000[diff] [blame]96 unsigned int dp_alloc_base;
97 unsigned int dp_alloc_top;
98#endif
Simon Glassf2d9aaf2012-12-13 20:49:02 +0000[diff] [blame]99#ifdef CONFIG_SYS_FPGA_COUNT
100 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
101#endif
Stefan Roeseb47a63d2015-10-02 08:20:35 +0200[diff] [blame]102#if defined(CONFIG_WD_MAX_RATE)
103 unsigned long long wdt_last; /* trace watch-dog triggering rate */
104#endif
105#if defined(CONFIG_LWMON5)
106 unsigned long kbd_status;
107#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]108};
109
Simon Glass1c62cc22012-12-13 20:49:23 +0000[diff] [blame]110#include <asm-generic/global_data.h>
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]111
112#if 1
Wolfgang Denk69c09642008-02-14 22:43:22 +0100[diff] [blame]113#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]114#else /* We could use plain global data, but the resulting code is bigger */
115#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
116#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
117 gd_t *gd
118#endif
119
120#endif /* __ASM_GBL_DATA_H */