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git01.mediatek.com / filogic / uboot / 38502ebb25499a827d6596ee5f3522ca15056bfd / . / configs / maxbcm_defconfig
blob: 54f2c14aa0cf89e4047b2a55df6746587d7ec91b [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_ARM=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]2CONFIG_ARCH_CPU_INIT=y
Stefan Roese383e0c12015-08-25 13:18:38 +0200[diff] [blame]3CONFIG_ARCH_MVEBU=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x00800000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]5CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]6CONFIG_SPL_LIBGENERIC_SUPPORT=y
Masahiro Yamada75794f92016-09-19 21:40:26 +0900[diff] [blame]7CONFIG_SYS_MALLOC_F_LEN=0x2000
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]8CONFIG_TARGET_MAXBCM=y
Simon Glasse076d6f2016-09-12 23:18:56 -0600[diff] [blame]9CONFIG_SPL_SERIAL_SUPPORT=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]10CONFIG_NR_DRAM_BANKS=2
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_SPL=y
12CONFIG_DEBUG_UART_BASE=0xd0012000
13CONFIG_DEBUG_UART_CLOCK=250000000
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]14CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]15CONFIG_SPL_SPI_SUPPORT=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]16CONFIG_DEBUG_UART=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]17CONFIG_BOOTDELAY=3
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]18CONFIG_USE_PREBOOT=y
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]19CONFIG_SYS_CONSOLE_INFO_QUIET=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]20# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]21CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Goldschmidtcc4078c2018-09-30 14:31:53 +0200[diff] [blame]22CONFIG_SPL_TEXT_BASE=0x40004030
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]23CONFIG_SPL_I2C_SUPPORT=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]24CONFIG_SPL_SPI_LOAD=y
Hannes Schmelzer38df9972019-08-22 15:41:46 +0200[diff] [blame]25CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]26# CONFIG_CMD_FLASH is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]27CONFIG_CMD_I2C=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]28CONFIG_CMD_SF=y
29CONFIG_CMD_SPI=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]30# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]31CONFIG_CMD_DHCP=y
Tom Rinie8f8d672018-04-17 09:22:31 -0400[diff] [blame]32CONFIG_CMD_TFTPPUT=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]33CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]34CONFIG_CMD_PING=y
35CONFIG_CMD_TIME=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]36CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
Patrick Delaunayf8e932e2019-02-27 15:20:38 +0100[diff] [blame]37CONFIG_USE_ENV_SPI_MAX_HZ=y
38CONFIG_ENV_SPI_MAX_HZ=50000000
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]39CONFIG_SPL_OF_TRANSLATE=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]40# CONFIG_MMC is not set
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]41CONFIG_SPI_FLASH=y
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]42CONFIG_SPI_FLASH_MACRONIX=y
43CONFIG_SPI_FLASH_SPANSION=y
44CONFIG_SPI_FLASH_STMICRO=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]45CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]46CONFIG_PHY_GIGE=y
Chris Packham919041c2017-08-21 20:17:03 +1200[diff] [blame]47CONFIG_MVNETA=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]48CONFIG_MII=y
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]49CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]50CONFIG_SYS_NS16550=y
Tuomas Tynkkynen13b5cb82018-02-07 02:42:22 +0200[diff] [blame]51CONFIG_KIRKWOOD_SPI=y