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git01.mediatek.com / filogic / uboot / 3845660bfe98ace7613ba924fc984dd27ba6f80a / . / board / is1 / qts / sdram_config.h
blob: 67ea1ec21e7018873b9709f75afa7dc00553f72a [file] [log] [blame]
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]1/*
2 * Altera SoCFPGA SDRAM configuration
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __SOCFPGA_SDRAM_CONFIG_H__
8#define __SOCFPGA_SDRAM_CONFIG_H__
9
10/* SDRAM configuration */
11#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
19#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
20#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
21#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
22#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
23#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
24#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1
25#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
26#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
27#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
28#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
29#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
30#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16
31#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
32#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
34#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
35#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
36#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
37#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
38#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64
39#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
40#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
41#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
42#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
43#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
44#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
45#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
46#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
47#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
48#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
49#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
50#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
51#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
52#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
53#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
54#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
55#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
56#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
57#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
58#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
59#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
60#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
61#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
62#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
63#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
64#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
65#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
66#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
67#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
68#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
69#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
70#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
71#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
72#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
73#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
74#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
75#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
76#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
77#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
78
79/* Sequencer auto configuration */
80#define RW_MGR_ACTIVATE_0_AND_1 0x0D
81#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
82#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
83#define RW_MGR_ACTIVATE_1 0x0F
84#define RW_MGR_CLEAR_DQS_ENABLE 0x49
85#define RW_MGR_GUARANTEED_READ 0x4C
86#define RW_MGR_GUARANTEED_READ_CONT 0x54
87#define RW_MGR_GUARANTEED_WRITE 0x18
88#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
89#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
90#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
91#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
92#define RW_MGR_IDLE 0x00
93#define RW_MGR_IDLE_LOOP1 0x7B
94#define RW_MGR_IDLE_LOOP2 0x7A
95#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
96#define RW_MGR_INIT_RESET_1_CKE_0 0x74
97#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
98#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
99#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
100#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
101#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
102#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
103#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
104#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
105#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
106#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
107#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
108#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
109#define RW_MGR_MRS0_DLL_RESET 0x02
110#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
111#define RW_MGR_MRS0_USER 0x07
112#define RW_MGR_MRS0_USER_MIRR 0x0C
113#define RW_MGR_MRS1 0x03
114#define RW_MGR_MRS1_MIRR 0x09
115#define RW_MGR_MRS2 0x04
116#define RW_MGR_MRS2_MIRR 0x0A
117#define RW_MGR_MRS3 0x05
118#define RW_MGR_MRS3_MIRR 0x0B
119#define RW_MGR_PRECHARGE_ALL 0x12
120#define RW_MGR_READ_B2B 0x59
121#define RW_MGR_READ_B2B_WAIT1 0x61
122#define RW_MGR_READ_B2B_WAIT2 0x6B
123#define RW_MGR_REFRESH_ALL 0x14
124#define RW_MGR_RETURN 0x01
125#define RW_MGR_SGLE_READ 0x7D
126#define RW_MGR_ZQCL 0x06
127
128/* Sequencer defines configuration */
129#define AFI_RATE_RATIO 1
130#define CALIB_LFIFO_OFFSET 8
131#define CALIB_VFIFO_OFFSET 6
132#define ENABLE_SUPER_QUICK_CALIBRATION 0
133#define IO_DELAY_PER_DCHAIN_TAP 25
134#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
135#define IO_DELAY_PER_OPA_TAP 312
136#define IO_DLL_CHAIN_LENGTH 8
137#define IO_DQDQS_OUT_PHASE_MAX 0
138#define IO_DQS_EN_DELAY_MAX 31
139#define IO_DQS_EN_DELAY_OFFSET 0
140#define IO_DQS_EN_PHASE_MAX 7
141#define IO_DQS_IN_DELAY_MAX 31
142#define IO_DQS_IN_RESERVE 4
143#define IO_DQS_OUT_RESERVE 4
144#define IO_IO_IN_DELAY_MAX 31
145#define IO_IO_OUT1_DELAY_MAX 31
146#define IO_IO_OUT2_DELAY_MAX 0
147#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
148#define MAX_LATENCY_COUNT_WIDTH 5
149#define READ_VALID_FIFO_SIZE 16
150#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
151#define RW_MGR_MEM_ADDRESS_MIRRORING 0
152#define RW_MGR_MEM_DATA_MASK_WIDTH 2
153#define RW_MGR_MEM_DATA_WIDTH 16
154#define RW_MGR_MEM_DQ_PER_READ_DQS 8
155#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
156#define RW_MGR_MEM_IF_READ_DQS_WIDTH 2
157#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 2
158#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
159#define RW_MGR_MEM_NUMBER_OF_RANKS 1
160#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
161#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
162#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 2
163#define TINIT_CNTR0_VAL 99
164#define TINIT_CNTR1_VAL 32
165#define TINIT_CNTR2_VAL 32
166#define TRESET_CNTR0_VAL 99
167#define TRESET_CNTR1_VAL 99
168#define TRESET_CNTR2_VAL 10
169
170/* Sequencer ac_rom_init configuration */
171const u32 ac_rom_init[] = {
172 0x20700000,
173 0x20780000,
174 0x10080431,
175 0x10080530,
176 0x10090044,
177 0x100a00c8,
178 0x100b0000,
179 0x10380400,
180 0x10080449,
181 0x100804c8,
182 0x100a0024,
183 0x10090130,
184 0x100b0000,
185 0x30780000,
186 0x38780000,
187 0x30780000,
188 0x10680000,
189 0x106b0000,
190 0x10280400,
191 0x10480000,
192 0x1c980000,
193 0x1c9b0000,
194 0x1c980008,
195 0x1c9b0008,
196 0x38f80000,
197 0x3cf80000,
198 0x38780000,
199 0x18180000,
200 0x18980000,
201 0x13580000,
202 0x135b0000,
203 0x13580008,
204 0x135b0008,
205 0x33780000,
206 0x10580008,
207 0x10780000
208};
209
210/* Sequencer inst_rom_init configuration */
211const u32 inst_rom_init[] = {
212 0x80000,
213 0x80680,
214 0x8180,
215 0x8200,
216 0x8280,
217 0x8300,
218 0x8380,
219 0x8100,
220 0x8480,
221 0x8500,
222 0x8580,
223 0x8600,
224 0x8400,
225 0x800,
226 0x8680,
227 0x880,
228 0xa680,
229 0x80680,
230 0x900,
231 0x80680,
232 0x980,
233 0xa680,
234 0x8680,
235 0x80680,
236 0xb68,
237 0xcce8,
238 0xae8,
239 0x8ce8,
240 0xb88,
241 0xec88,
242 0xa08,
243 0xac88,
244 0x80680,
245 0xce00,
246 0xcd80,
247 0xe700,
248 0xc00,
249 0x20ce0,
250 0x20ce0,
251 0x20ce0,
252 0x20ce0,
253 0xd00,
254 0x680,
255 0x680,
256 0x680,
257 0x680,
258 0x60e80,
259 0x61080,
260 0x61080,
261 0x61080,
262 0xa680,
263 0x8680,
264 0x80680,
265 0xce00,
266 0xcd80,
267 0xe700,
268 0xc00,
269 0x30ce0,
270 0x30ce0,
271 0x30ce0,
272 0x30ce0,
273 0xd00,
274 0x680,
275 0x680,
276 0x680,
277 0x680,
278 0x70e80,
279 0x71080,
280 0x71080,
281 0x71080,
282 0xa680,
283 0x8680,
284 0x80680,
285 0x1158,
286 0x6d8,
287 0x80680,
288 0x1168,
289 0x7e8,
290 0x7e8,
291 0x87e8,
292 0x40fe8,
293 0x410e8,
294 0x410e8,
295 0x410e8,
296 0x1168,
297 0x7e8,
298 0x7e8,
299 0xa7e8,
300 0x80680,
301 0x40e88,
302 0x41088,
303 0x41088,
304 0x41088,
305 0x40f68,
306 0x410e8,
307 0x410e8,
308 0x410e8,
309 0xa680,
310 0x40fe8,
311 0x410e8,
312 0x410e8,
313 0x410e8,
314 0x41008,
315 0x41088,
316 0x41088,
317 0x41088,
318 0x1100,
319 0xc680,
320 0x8680,
321 0xe680,
322 0x80680,
323 0x0,
324 0x8000,
325 0xa000,
326 0xc000,
327 0x80000,
328 0x80,
329 0x8080,
330 0xa080,
331 0xc080,
332 0x80080,
333 0x9180,
334 0x8680,
335 0xa680,
336 0x80680,
337 0x40f08,
338 0x80680
339};
340
341#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */