Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the esd TASREG board. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * board/config.h - configuration options, board specific |
| 11 | */ |
| 12 | |
| 13 | #ifndef _M5249EVB_H |
| 14 | #define _M5249EVB_H |
| 15 | |
| 16 | /* |
| 17 | * High Level Configuration Options |
| 18 | * (easy to change) |
| 19 | */ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 20 | #define CONFIG_MCFTMR |
| 21 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 22 | #define CONFIG_SYS_UART_PORT (0) |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 23 | |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 24 | #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ |
| 25 | |
| 26 | /* |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 27 | * Clock configuration: enable only one of the following options |
| 28 | */ |
| 29 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 30 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
| 31 | #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ |
| 32 | #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 33 | |
| 34 | /* |
| 35 | * Low Level Configuration Settings |
| 36 | * (address mappings, register initial values, etc.) |
| 37 | * You should know what you are doing if you make changes here. |
| 38 | */ |
| 39 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 40 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
| 41 | #define CONFIG_SYS_MBAR2 0x80000000 |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 42 | |
| 43 | /*----------------------------------------------------------------------- |
| 44 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 45 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 48 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 50 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 51 | #define LDS_BOARD_TEXT \ |
Simon Glass | 547cb40 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 52 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 53 | env/embedded.o(.text); |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 54 | |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 55 | /*----------------------------------------------------------------------- |
| 56 | * Start addresses for the final memory configuration |
| 57 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 58 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 59 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 60 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 61 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 62 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 63 | |
| 64 | #if 0 /* test-only */ |
| 65 | #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ |
| 66 | #endif |
| 67 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 69 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 70 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * For booting Linux, the board info and command line data |
| 75 | * have to be in the first 8 MB of memory, since this is |
| 76 | * the maximum mapped by the Linux kernel during initialization ?? |
| 77 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 79 | |
| 80 | /*----------------------------------------------------------------------- |
| 81 | * FLASH organization |
| 82 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 83 | #ifdef CONFIG_SYS_FLASH_CFI |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 84 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
| 86 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | # define CONFIG_SYS_FLASH_CHECKSUM |
| 89 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 90 | #endif |
| 91 | |
| 92 | /*----------------------------------------------------------------------- |
| 93 | * Cache Configuration |
| 94 | */ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 95 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 96 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 97 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 98 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 99 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 100 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
| 101 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ |
| 102 | CF_ADDRMASK(2) | \ |
| 103 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 104 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ |
| 105 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 106 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 107 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ |
| 108 | CF_CACR_DBWE) |
| 109 | |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 110 | /*----------------------------------------------------------------------- |
| 111 | * Memory bank definitions |
| 112 | */ |
| 113 | |
| 114 | /* CS0 - AMD Flash, address 0xffc00000 */ |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 115 | #define CONFIG_SYS_CS0_BASE 0xffe00000 |
| 116 | #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 117 | /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 118 | #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 119 | |
| 120 | /* CS1 - FPGA, address 0xe0000000 */ |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 121 | #define CONFIG_SYS_CS1_BASE 0xe0000000 |
| 122 | #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ |
| 123 | #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 124 | |
| 125 | /*----------------------------------------------------------------------- |
| 126 | * Port configuration |
| 127 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
| 129 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ |
| 130 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ |
| 131 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
| 132 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
| 133 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
| 134 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ |
TsiChungLiew | ade32cd | 2007-08-16 05:04:31 -0500 | [diff] [blame] | 135 | |
| 136 | #endif /* M5249 */ |