Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 2 | /* |
Patrice Chotard | 789ee0e | 2017-10-23 09:53:58 +0200 | [diff] [blame] | 3 | * Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
| 4 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CONFIG_H |
| 8 | #define __CONFIG_H |
| 9 | |
Patrice Chotard | 44d75ac | 2020-02-03 15:10:40 +0100 | [diff] [blame] | 10 | #include <linux/sizes.h> |
| 11 | |
| 12 | /* For booting Linux, use the first 6MB of memory */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 13 | #define CFG_SYS_BOOTMAPSZ SZ_4M + SZ_2M |
Patrice Chotard | 44d75ac | 2020-02-03 15:10:40 +0100 | [diff] [blame] | 14 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 15 | #define CFG_SYS_FLASH_BASE 0x08000000 |
Vikas Manocha | 50218ae | 2017-05-28 12:55:10 -0700 | [diff] [blame] | 16 | |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 17 | /* |
| 18 | * Configuration of the external SDRAM memory |
| 19 | */ |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 20 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 21 | #define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 22 | |
Patrice Chotard | 231902c | 2019-02-21 10:07:54 +0100 | [diff] [blame] | 23 | #define BOOT_TARGET_DEVICES(func) \ |
| 24 | func(MMC, mmc, 0) |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 25 | |
Patrice Chotard | 231902c | 2019-02-21 10:07:54 +0100 | [diff] [blame] | 26 | #include <config_distro_bootcmd.h> |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 27 | #define CFG_EXTRA_ENV_SETTINGS \ |
Patrice Chotard | 231902c | 2019-02-21 10:07:54 +0100 | [diff] [blame] | 28 | "kernel_addr_r=0xC0008000\0" \ |
Patrice Chotard | f4697d1 | 2022-04-27 13:53:58 +0200 | [diff] [blame] | 29 | "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0" \ |
Patrice Chotard | 0c6aee5 | 2020-02-03 15:10:39 +0100 | [diff] [blame] | 30 | "fdt_addr_r=0xC0408000\0" \ |
| 31 | "scriptaddr=0xC0418000\0" \ |
| 32 | "pxefile_addr_r=0xC0428000\0" \ |
| 33 | "ramdisk_addr_r=0xC0438000\0" \ |
Patrice Chotard | 231902c | 2019-02-21 10:07:54 +0100 | [diff] [blame] | 34 | BOOTENV |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 35 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 36 | #define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ |
Tom Rini | daf811e | 2022-05-27 15:18:06 -0400 | [diff] [blame] | 37 | CONFIG_SPL_PAD_TO) |
Vikas Manocha | b785bb4 | 2017-05-28 12:55:13 -0700 | [diff] [blame] | 38 | |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 39 | #endif /* __CONFIG_H */ |