blob: 38727a271b282e8e0deecea17c95f605aeba9d8d [file] [log] [blame]
developer3f7834c2023-07-19 17:17:54 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7988.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 model = "mt7988-rfb";
13 compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
14
15 chosen {
16 stdout-path = &uart0;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 reg_3p3v: regulator-3p3v {
25 compatible = "regulator-fixed";
26 regulator-name = "fixed-3.3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-boot-on;
30 regulator-always-on;
31 };
32};
33
34&uart0 {
35 status = "okay";
36};
37
38&i2c1 {
39 pinctrl-names = "default";
40 pinctrl-0 = <&i2c1_pins>;
41 status = "okay";
42};
43
developer3831fef2025-01-17 17:18:27 +080044&eth0 {
developer3f7834c2023-07-19 17:17:54 +080045 status = "okay";
developer3f7834c2023-07-19 17:17:54 +080046 phy-mode = "usxgmii";
47 mediatek,switch = "mt7988";
48
49 fixed-link {
developer540a4da2025-01-17 17:18:22 +080050 speed = <10000>;
developer3f7834c2023-07-19 17:17:54 +080051 full-duplex;
52 pause;
53 };
54};
55
56&pinctrl {
57 i2c1_pins: i2c1-pins {
58 mux {
59 function = "i2c";
60 groups = "i2c1_0";
61 };
62 };
63
64 pwm_pins: pwm-pins {
65 mux {
66 function = "pwm";
67 groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
68 "pwm5", "pwm6", "pwm7";
69 };
70 };
71
72 spi0_pins: spi0-pins {
73 mux {
74 function = "spi";
75 groups = "spi0", "spi0_wp_hold";
76 };
77 };
78
79 mmc1_pins_default: mmc1default {
80 mux {
81 function = "flash";
82 groups = "emmc_45";
83 };
84
85 conf-cmd-dat {
86 pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
87 "SPI2_CLK", "SPI2_HOLD";
88 input-enable;
developer4c813af2024-01-22 10:07:54 +080089 drive-strength = <MTK_DRIVE_4mA>;
developer3f7834c2023-07-19 17:17:54 +080090 };
91
92 conf-clk {
93 pins = "SPI2_WP";
developer4c813af2024-01-22 10:07:54 +080094 drive-strength = <MTK_DRIVE_4mA>;
developer3f7834c2023-07-19 17:17:54 +080095 };
96 };
97};
98
99&pwm {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pwm_pins>;
102 status = "okay";
103};
104
105&spi0 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&spi0_pins>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 status = "okay";
111 must_tx;
112 enhance_timing;
113 dma_ext;
114 ipm_design;
115 support_quad;
116 tick_dly = <2>;
117 sample_sel = <0>;
118
119 spi_nand@0 {
120 compatible = "spi-nand";
121 reg = <0>;
122 spi-max-frequency = <52000000>;
123 };
124};
125
126&mmc0 {
127 pinctrl-names = "default";
128 pinctrl-0 = <&mmc1_pins_default>;
129 max-frequency = <52000000>;
130 bus-width = <4>;
131 cap-sd-highspeed;
132 vmmc-supply = <&reg_3p3v>;
133 vqmmc-supply = <&reg_3p3v>;
134 status = "okay";
135};