Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 2 | /* |
| 3 | * MUSB OTG driver host support |
| 4 | * |
| 5 | * Copyright 2005 Mentor Graphics Corporation |
| 6 | * Copyright (C) 2005-2006 by Texas Instruments |
| 7 | * Copyright (C) 2006-2007 Nokia Corporation |
| 8 | * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 11 | #ifndef __UBOOT__ |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 12 | #include <dm/device_compat.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 13 | #include <dm/devres.h> |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/sched.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/errno.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/list.h> |
| 22 | #include <linux/dma-mapping.h> |
| 23 | #else |
| 24 | #include <common.h> |
Sean Anderson | 3e46486 | 2020-10-04 21:39:54 -0400 | [diff] [blame] | 25 | #include <dm.h> |
| 26 | #include <dm/device_compat.h> |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 27 | #include <usb.h> |
Simon Glass | c06c1be | 2020-05-10 11:40:08 -0600 | [diff] [blame] | 28 | #include <linux/bug.h> |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 29 | #include "linux-compat.h" |
| 30 | #include "usb-compat.h" |
| 31 | #endif |
| 32 | |
| 33 | #include "musb_core.h" |
| 34 | #include "musb_host.h" |
| 35 | |
| 36 | |
| 37 | /* MUSB HOST status 22-mar-2006 |
| 38 | * |
| 39 | * - There's still lots of partial code duplication for fault paths, so |
| 40 | * they aren't handled as consistently as they need to be. |
| 41 | * |
| 42 | * - PIO mostly behaved when last tested. |
| 43 | * + including ep0, with all usbtest cases 9, 10 |
| 44 | * + usbtest 14 (ep0out) doesn't seem to run at all |
| 45 | * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest |
| 46 | * configurations, but otherwise double buffering passes basic tests. |
| 47 | * + for 2.6.N, for N > ~10, needs API changes for hcd framework. |
| 48 | * |
| 49 | * - DMA (CPPI) ... partially behaves, not currently recommended |
| 50 | * + about 1/15 the speed of typical EHCI implementations (PCI) |
| 51 | * + RX, all too often reqpkt seems to misbehave after tx |
| 52 | * + TX, no known issues (other than evident silicon issue) |
| 53 | * |
| 54 | * - DMA (Mentor/OMAP) ...has at least toggle update problems |
| 55 | * |
| 56 | * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet |
| 57 | * starvation ... nothing yet for TX, interrupt, or bulk. |
| 58 | * |
| 59 | * - Not tested with HNP, but some SRP paths seem to behave. |
| 60 | * |
| 61 | * NOTE 24-August-2006: |
| 62 | * |
| 63 | * - Bulk traffic finally uses both sides of hardware ep1, freeing up an |
| 64 | * extra endpoint for periodic use enabling hub + keybd + mouse. That |
| 65 | * mostly works, except that with "usbnet" it's easy to trigger cases |
| 66 | * with "ping" where RX loses. (a) ping to davinci, even "ping -f", |
| 67 | * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses |
| 68 | * although ARP RX wins. (That test was done with a full speed link.) |
| 69 | */ |
| 70 | |
| 71 | |
| 72 | /* |
| 73 | * NOTE on endpoint usage: |
| 74 | * |
| 75 | * CONTROL transfers all go through ep0. BULK ones go through dedicated IN |
| 76 | * and OUT endpoints ... hardware is dedicated for those "async" queue(s). |
| 77 | * (Yes, bulk _could_ use more of the endpoints than that, and would even |
| 78 | * benefit from it.) |
| 79 | * |
| 80 | * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. |
| 81 | * So far that scheduling is both dumb and optimistic: the endpoint will be |
| 82 | * "claimed" until its software queue is no longer refilled. No multiplexing |
| 83 | * of transfers between endpoints, or anything clever. |
| 84 | */ |
| 85 | |
| 86 | |
| 87 | static void musb_ep_program(struct musb *musb, u8 epnum, |
| 88 | struct urb *urb, int is_out, |
| 89 | u8 *buf, u32 offset, u32 len); |
| 90 | |
| 91 | /* |
| 92 | * Clear TX fifo. Needed to avoid BABBLE errors. |
| 93 | */ |
| 94 | static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) |
| 95 | { |
| 96 | struct musb *musb = ep->musb; |
| 97 | void __iomem *epio = ep->regs; |
| 98 | u16 csr; |
| 99 | u16 lastcsr = 0; |
| 100 | int retries = 1000; |
| 101 | |
| 102 | csr = musb_readw(epio, MUSB_TXCSR); |
| 103 | while (csr & MUSB_TXCSR_FIFONOTEMPTY) { |
| 104 | if (csr != lastcsr) |
| 105 | dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); |
| 106 | lastcsr = csr; |
| 107 | csr |= MUSB_TXCSR_FLUSHFIFO; |
| 108 | musb_writew(epio, MUSB_TXCSR, csr); |
| 109 | csr = musb_readw(epio, MUSB_TXCSR); |
| 110 | if (WARN(retries-- < 1, |
| 111 | "Could not flush host TX%d fifo: csr: %04x\n", |
| 112 | ep->epnum, csr)) |
| 113 | return; |
| 114 | mdelay(1); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) |
| 119 | { |
| 120 | void __iomem *epio = ep->regs; |
| 121 | u16 csr; |
| 122 | int retries = 5; |
| 123 | |
| 124 | /* scrub any data left in the fifo */ |
| 125 | do { |
| 126 | csr = musb_readw(epio, MUSB_TXCSR); |
| 127 | if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) |
| 128 | break; |
| 129 | musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); |
| 130 | csr = musb_readw(epio, MUSB_TXCSR); |
| 131 | udelay(10); |
| 132 | } while (--retries); |
| 133 | |
| 134 | WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", |
| 135 | ep->epnum, csr); |
| 136 | |
| 137 | /* and reset for the next transfer */ |
| 138 | musb_writew(epio, MUSB_TXCSR, 0); |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * Start transmit. Caller is responsible for locking shared resources. |
| 143 | * musb must be locked. |
| 144 | */ |
| 145 | static inline void musb_h_tx_start(struct musb_hw_ep *ep) |
| 146 | { |
| 147 | u16 txcsr; |
| 148 | |
| 149 | /* NOTE: no locks here; caller should lock and select EP */ |
| 150 | if (ep->epnum) { |
| 151 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); |
| 152 | txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; |
| 153 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); |
| 154 | } else { |
| 155 | txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; |
| 156 | musb_writew(ep->regs, MUSB_CSR0, txcsr); |
| 157 | } |
| 158 | |
| 159 | } |
| 160 | |
| 161 | static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) |
| 162 | { |
| 163 | u16 txcsr; |
| 164 | |
| 165 | /* NOTE: no locks here; caller should lock and select EP */ |
| 166 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); |
| 167 | txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; |
| 168 | if (is_cppi_enabled()) |
| 169 | txcsr |= MUSB_TXCSR_DMAMODE; |
| 170 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); |
| 171 | } |
| 172 | |
| 173 | static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) |
| 174 | { |
| 175 | if (is_in != 0 || ep->is_shared_fifo) |
| 176 | ep->in_qh = qh; |
| 177 | if (is_in == 0 || ep->is_shared_fifo) |
| 178 | ep->out_qh = qh; |
| 179 | } |
| 180 | |
| 181 | static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) |
| 182 | { |
| 183 | return is_in ? ep->in_qh : ep->out_qh; |
| 184 | } |
| 185 | |
| 186 | /* |
| 187 | * Start the URB at the front of an endpoint's queue |
| 188 | * end must be claimed from the caller. |
| 189 | * |
| 190 | * Context: controller locked, irqs blocked |
| 191 | */ |
| 192 | static void |
| 193 | musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) |
| 194 | { |
| 195 | u16 frame; |
| 196 | u32 len; |
| 197 | void __iomem *mbase = musb->mregs; |
| 198 | struct urb *urb = next_urb(qh); |
| 199 | void *buf = urb->transfer_buffer; |
| 200 | u32 offset = 0; |
| 201 | struct musb_hw_ep *hw_ep = qh->hw_ep; |
| 202 | unsigned pipe = urb->pipe; |
| 203 | u8 address = usb_pipedevice(pipe); |
| 204 | int epnum = hw_ep->epnum; |
| 205 | |
| 206 | /* initialize software qh state */ |
| 207 | qh->offset = 0; |
| 208 | qh->segsize = 0; |
| 209 | |
| 210 | /* gather right source of data */ |
| 211 | switch (qh->type) { |
| 212 | case USB_ENDPOINT_XFER_CONTROL: |
| 213 | /* control transfers always start with SETUP */ |
| 214 | is_in = 0; |
| 215 | musb->ep0_stage = MUSB_EP0_START; |
| 216 | buf = urb->setup_packet; |
| 217 | len = 8; |
| 218 | break; |
| 219 | #ifndef __UBOOT__ |
| 220 | case USB_ENDPOINT_XFER_ISOC: |
| 221 | qh->iso_idx = 0; |
| 222 | qh->frame = 0; |
| 223 | offset = urb->iso_frame_desc[0].offset; |
| 224 | len = urb->iso_frame_desc[0].length; |
| 225 | break; |
| 226 | #endif |
| 227 | default: /* bulk, interrupt */ |
| 228 | /* actual_length may be nonzero on retry paths */ |
| 229 | buf = urb->transfer_buffer + urb->actual_length; |
| 230 | len = urb->transfer_buffer_length - urb->actual_length; |
| 231 | } |
| 232 | |
| 233 | dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", |
| 234 | qh, urb, address, qh->epnum, |
| 235 | is_in ? "in" : "out", |
| 236 | ({char *s; switch (qh->type) { |
| 237 | case USB_ENDPOINT_XFER_CONTROL: s = ""; break; |
| 238 | case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; |
| 239 | #ifndef __UBOOT__ |
| 240 | case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; |
| 241 | #endif |
| 242 | default: s = "-intr"; break; |
| 243 | }; s; }), |
| 244 | epnum, buf + offset, len); |
| 245 | |
| 246 | /* Configure endpoint */ |
| 247 | musb_ep_set_qh(hw_ep, is_in, qh); |
| 248 | musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); |
| 249 | |
| 250 | /* transmit may have more work: start it when it is time */ |
| 251 | if (is_in) |
| 252 | return; |
| 253 | |
| 254 | /* determine if the time is right for a periodic transfer */ |
| 255 | switch (qh->type) { |
| 256 | #ifndef __UBOOT__ |
| 257 | case USB_ENDPOINT_XFER_ISOC: |
| 258 | #endif |
| 259 | case USB_ENDPOINT_XFER_INT: |
| 260 | dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); |
| 261 | frame = musb_readw(mbase, MUSB_FRAME); |
| 262 | /* FIXME this doesn't implement that scheduling policy ... |
| 263 | * or handle framecounter wrapping |
| 264 | */ |
| 265 | #ifndef __UBOOT__ |
| 266 | if ((urb->transfer_flags & URB_ISO_ASAP) |
| 267 | || (frame >= urb->start_frame)) { |
| 268 | /* REVISIT the SOF irq handler shouldn't duplicate |
| 269 | * this code; and we don't init urb->start_frame... |
| 270 | */ |
| 271 | qh->frame = 0; |
| 272 | goto start; |
| 273 | } else { |
| 274 | #endif |
| 275 | qh->frame = urb->start_frame; |
| 276 | /* enable SOF interrupt so we can count down */ |
| 277 | dev_dbg(musb->controller, "SOF for %d\n", epnum); |
| 278 | #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ |
| 279 | musb_writeb(mbase, MUSB_INTRUSBE, 0xff); |
| 280 | #endif |
| 281 | #ifndef __UBOOT__ |
| 282 | } |
| 283 | #endif |
| 284 | break; |
| 285 | default: |
| 286 | start: |
| 287 | dev_dbg(musb->controller, "Start TX%d %s\n", epnum, |
| 288 | hw_ep->tx_channel ? "dma" : "pio"); |
| 289 | |
| 290 | if (!hw_ep->tx_channel) |
| 291 | musb_h_tx_start(hw_ep); |
| 292 | else if (is_cppi_enabled() || tusb_dma_omap()) |
| 293 | musb_h_tx_dma_start(hw_ep); |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | /* Context: caller owns controller lock, IRQs are blocked */ |
| 298 | static void musb_giveback(struct musb *musb, struct urb *urb, int status) |
| 299 | __releases(musb->lock) |
| 300 | __acquires(musb->lock) |
| 301 | { |
| 302 | dev_dbg(musb->controller, |
| 303 | "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", |
| 304 | urb, urb->complete, status, |
| 305 | usb_pipedevice(urb->pipe), |
| 306 | usb_pipeendpoint(urb->pipe), |
| 307 | usb_pipein(urb->pipe) ? "in" : "out", |
| 308 | urb->actual_length, urb->transfer_buffer_length |
| 309 | ); |
| 310 | |
| 311 | usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); |
| 312 | spin_unlock(&musb->lock); |
| 313 | usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); |
| 314 | spin_lock(&musb->lock); |
| 315 | } |
| 316 | |
| 317 | /* For bulk/interrupt endpoints only */ |
| 318 | static inline void musb_save_toggle(struct musb_qh *qh, int is_in, |
| 319 | struct urb *urb) |
| 320 | { |
| 321 | void __iomem *epio = qh->hw_ep->regs; |
| 322 | u16 csr; |
| 323 | |
| 324 | /* |
| 325 | * FIXME: the current Mentor DMA code seems to have |
| 326 | * problems getting toggle correct. |
| 327 | */ |
| 328 | |
| 329 | if (is_in) |
| 330 | csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; |
| 331 | else |
| 332 | csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; |
| 333 | |
| 334 | usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); |
| 335 | } |
| 336 | |
| 337 | /* |
| 338 | * Advance this hardware endpoint's queue, completing the specified URB and |
| 339 | * advancing to either the next URB queued to that qh, or else invalidating |
| 340 | * that qh and advancing to the next qh scheduled after the current one. |
| 341 | * |
| 342 | * Context: caller owns controller lock, IRQs are blocked |
| 343 | */ |
| 344 | static void musb_advance_schedule(struct musb *musb, struct urb *urb, |
| 345 | struct musb_hw_ep *hw_ep, int is_in) |
| 346 | { |
| 347 | struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); |
| 348 | struct musb_hw_ep *ep = qh->hw_ep; |
| 349 | int ready = qh->is_ready; |
| 350 | int status; |
| 351 | |
| 352 | status = (urb->status == -EINPROGRESS) ? 0 : urb->status; |
| 353 | |
| 354 | /* save toggle eagerly, for paranoia */ |
| 355 | switch (qh->type) { |
| 356 | case USB_ENDPOINT_XFER_BULK: |
| 357 | case USB_ENDPOINT_XFER_INT: |
| 358 | musb_save_toggle(qh, is_in, urb); |
| 359 | break; |
| 360 | #ifndef __UBOOT__ |
| 361 | case USB_ENDPOINT_XFER_ISOC: |
| 362 | if (status == 0 && urb->error_count) |
| 363 | status = -EXDEV; |
| 364 | break; |
| 365 | #endif |
| 366 | } |
| 367 | |
| 368 | qh->is_ready = 0; |
| 369 | musb_giveback(musb, urb, status); |
| 370 | qh->is_ready = ready; |
| 371 | |
| 372 | /* reclaim resources (and bandwidth) ASAP; deschedule it, and |
| 373 | * invalidate qh as soon as list_empty(&hep->urb_list) |
| 374 | */ |
| 375 | if (list_empty(&qh->hep->urb_list)) { |
| 376 | struct list_head *head; |
| 377 | struct dma_controller *dma = musb->dma_controller; |
| 378 | |
| 379 | if (is_in) { |
| 380 | ep->rx_reinit = 1; |
| 381 | if (ep->rx_channel) { |
| 382 | dma->channel_release(ep->rx_channel); |
| 383 | ep->rx_channel = NULL; |
| 384 | } |
| 385 | } else { |
| 386 | ep->tx_reinit = 1; |
| 387 | if (ep->tx_channel) { |
| 388 | dma->channel_release(ep->tx_channel); |
| 389 | ep->tx_channel = NULL; |
| 390 | } |
| 391 | } |
| 392 | |
| 393 | /* Clobber old pointers to this qh */ |
| 394 | musb_ep_set_qh(ep, is_in, NULL); |
| 395 | qh->hep->hcpriv = NULL; |
| 396 | |
| 397 | switch (qh->type) { |
| 398 | |
| 399 | case USB_ENDPOINT_XFER_CONTROL: |
| 400 | case USB_ENDPOINT_XFER_BULK: |
| 401 | /* fifo policy for these lists, except that NAKing |
| 402 | * should rotate a qh to the end (for fairness). |
| 403 | */ |
| 404 | if (qh->mux == 1) { |
| 405 | head = qh->ring.prev; |
| 406 | list_del(&qh->ring); |
| 407 | kfree(qh); |
| 408 | qh = first_qh(head); |
| 409 | break; |
| 410 | } |
| 411 | |
| 412 | case USB_ENDPOINT_XFER_ISOC: |
| 413 | case USB_ENDPOINT_XFER_INT: |
| 414 | /* this is where periodic bandwidth should be |
| 415 | * de-allocated if it's tracked and allocated; |
| 416 | * and where we'd update the schedule tree... |
| 417 | */ |
| 418 | kfree(qh); |
| 419 | qh = NULL; |
| 420 | break; |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | if (qh != NULL && qh->is_ready) { |
| 425 | dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", |
| 426 | hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); |
| 427 | musb_start_urb(musb, is_in, qh); |
| 428 | } |
| 429 | } |
| 430 | |
| 431 | static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) |
| 432 | { |
| 433 | /* we don't want fifo to fill itself again; |
| 434 | * ignore dma (various models), |
| 435 | * leave toggle alone (may not have been saved yet) |
| 436 | */ |
| 437 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; |
| 438 | csr &= ~(MUSB_RXCSR_H_REQPKT |
| 439 | | MUSB_RXCSR_H_AUTOREQ |
| 440 | | MUSB_RXCSR_AUTOCLEAR); |
| 441 | |
| 442 | /* write 2x to allow double buffering */ |
| 443 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 444 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 445 | |
| 446 | /* flush writebuffer */ |
| 447 | return musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 448 | } |
| 449 | |
| 450 | /* |
| 451 | * PIO RX for a packet (or part of it). |
| 452 | */ |
| 453 | static bool |
| 454 | musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) |
| 455 | { |
| 456 | u16 rx_count; |
| 457 | u8 *buf; |
| 458 | u16 csr; |
| 459 | bool done = false; |
| 460 | u32 length; |
| 461 | int do_flush = 0; |
| 462 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 463 | void __iomem *epio = hw_ep->regs; |
| 464 | struct musb_qh *qh = hw_ep->in_qh; |
| 465 | int pipe = urb->pipe; |
| 466 | void *buffer = urb->transfer_buffer; |
| 467 | |
| 468 | /* musb_ep_select(mbase, epnum); */ |
| 469 | rx_count = musb_readw(epio, MUSB_RXCOUNT); |
| 470 | dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, |
| 471 | urb->transfer_buffer, qh->offset, |
| 472 | urb->transfer_buffer_length); |
| 473 | |
| 474 | /* unload FIFO */ |
| 475 | #ifndef __UBOOT__ |
| 476 | if (usb_pipeisoc(pipe)) { |
| 477 | int status = 0; |
| 478 | struct usb_iso_packet_descriptor *d; |
| 479 | |
| 480 | if (iso_err) { |
| 481 | status = -EILSEQ; |
| 482 | urb->error_count++; |
| 483 | } |
| 484 | |
| 485 | d = urb->iso_frame_desc + qh->iso_idx; |
| 486 | buf = buffer + d->offset; |
| 487 | length = d->length; |
| 488 | if (rx_count > length) { |
| 489 | if (status == 0) { |
| 490 | status = -EOVERFLOW; |
| 491 | urb->error_count++; |
| 492 | } |
| 493 | dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); |
| 494 | do_flush = 1; |
| 495 | } else |
| 496 | length = rx_count; |
| 497 | urb->actual_length += length; |
| 498 | d->actual_length = length; |
| 499 | |
| 500 | d->status = status; |
| 501 | |
| 502 | /* see if we are done */ |
| 503 | done = (++qh->iso_idx >= urb->number_of_packets); |
| 504 | } else { |
| 505 | #endif |
| 506 | /* non-isoch */ |
| 507 | buf = buffer + qh->offset; |
| 508 | length = urb->transfer_buffer_length - qh->offset; |
| 509 | if (rx_count > length) { |
| 510 | if (urb->status == -EINPROGRESS) |
| 511 | urb->status = -EOVERFLOW; |
| 512 | dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); |
| 513 | do_flush = 1; |
| 514 | } else |
| 515 | length = rx_count; |
| 516 | urb->actual_length += length; |
| 517 | qh->offset += length; |
| 518 | |
| 519 | /* see if we are done */ |
| 520 | done = (urb->actual_length == urb->transfer_buffer_length) |
| 521 | || (rx_count < qh->maxpacket) |
| 522 | || (urb->status != -EINPROGRESS); |
| 523 | if (done |
| 524 | && (urb->status == -EINPROGRESS) |
| 525 | && (urb->transfer_flags & URB_SHORT_NOT_OK) |
| 526 | && (urb->actual_length |
| 527 | < urb->transfer_buffer_length)) |
| 528 | urb->status = -EREMOTEIO; |
| 529 | #ifndef __UBOOT__ |
| 530 | } |
| 531 | #endif |
| 532 | |
| 533 | musb_read_fifo(hw_ep, length, buf); |
| 534 | |
| 535 | csr = musb_readw(epio, MUSB_RXCSR); |
| 536 | csr |= MUSB_RXCSR_H_WZC_BITS; |
| 537 | if (unlikely(do_flush)) |
| 538 | musb_h_flush_rxfifo(hw_ep, csr); |
| 539 | else { |
| 540 | /* REVISIT this assumes AUTOCLEAR is never set */ |
| 541 | csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); |
| 542 | if (!done) |
| 543 | csr |= MUSB_RXCSR_H_REQPKT; |
| 544 | musb_writew(epio, MUSB_RXCSR, csr); |
| 545 | } |
| 546 | |
| 547 | return done; |
| 548 | } |
| 549 | |
| 550 | /* we don't always need to reinit a given side of an endpoint... |
| 551 | * when we do, use tx/rx reinit routine and then construct a new CSR |
| 552 | * to address data toggle, NYET, and DMA or PIO. |
| 553 | * |
| 554 | * it's possible that driver bugs (especially for DMA) or aborting a |
| 555 | * transfer might have left the endpoint busier than it should be. |
| 556 | * the busy/not-empty tests are basically paranoia. |
| 557 | */ |
| 558 | static void |
| 559 | musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) |
| 560 | { |
| 561 | u16 csr; |
| 562 | |
| 563 | /* NOTE: we know the "rx" fifo reinit never triggers for ep0. |
| 564 | * That always uses tx_reinit since ep0 repurposes TX register |
| 565 | * offsets; the initial SETUP packet is also a kind of OUT. |
| 566 | */ |
| 567 | |
| 568 | /* if programmed for Tx, put it in RX mode */ |
| 569 | if (ep->is_shared_fifo) { |
| 570 | csr = musb_readw(ep->regs, MUSB_TXCSR); |
| 571 | if (csr & MUSB_TXCSR_MODE) { |
| 572 | musb_h_tx_flush_fifo(ep); |
| 573 | csr = musb_readw(ep->regs, MUSB_TXCSR); |
| 574 | musb_writew(ep->regs, MUSB_TXCSR, |
| 575 | csr | MUSB_TXCSR_FRCDATATOG); |
| 576 | } |
| 577 | |
| 578 | /* |
| 579 | * Clear the MODE bit (and everything else) to enable Rx. |
| 580 | * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. |
| 581 | */ |
| 582 | if (csr & MUSB_TXCSR_DMAMODE) |
| 583 | musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); |
| 584 | musb_writew(ep->regs, MUSB_TXCSR, 0); |
| 585 | |
| 586 | /* scrub all previous state, clearing toggle */ |
| 587 | } else { |
| 588 | csr = musb_readw(ep->regs, MUSB_RXCSR); |
| 589 | if (csr & MUSB_RXCSR_RXPKTRDY) |
| 590 | WARNING("rx%d, packet/%d ready?\n", ep->epnum, |
| 591 | musb_readw(ep->regs, MUSB_RXCOUNT)); |
| 592 | |
| 593 | musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); |
| 594 | } |
| 595 | |
| 596 | /* target addr and (for multipoint) hub addr/port */ |
| 597 | if (musb->is_multipoint) { |
| 598 | musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); |
| 599 | musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); |
| 600 | musb_write_rxhubport(ep->target_regs, qh->h_port_reg); |
| 601 | |
| 602 | } else |
| 603 | musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); |
| 604 | |
| 605 | /* protocol/endpoint, interval/NAKlimit, i/o size */ |
| 606 | musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); |
| 607 | musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); |
| 608 | /* NOTE: bulk combining rewrites high bits of maxpacket */ |
| 609 | /* Set RXMAXP with the FIFO size of the endpoint |
| 610 | * to disable double buffer mode. |
| 611 | */ |
| 612 | if (musb->double_buffer_not_ok) |
| 613 | musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); |
| 614 | else |
| 615 | musb_writew(ep->regs, MUSB_RXMAXP, |
| 616 | qh->maxpacket | ((qh->hb_mult - 1) << 11)); |
| 617 | |
| 618 | ep->rx_reinit = 0; |
| 619 | } |
| 620 | |
| 621 | static bool musb_tx_dma_program(struct dma_controller *dma, |
| 622 | struct musb_hw_ep *hw_ep, struct musb_qh *qh, |
| 623 | struct urb *urb, u32 offset, u32 length) |
| 624 | { |
| 625 | struct dma_channel *channel = hw_ep->tx_channel; |
| 626 | void __iomem *epio = hw_ep->regs; |
| 627 | u16 pkt_size = qh->maxpacket; |
| 628 | u16 csr; |
| 629 | u8 mode; |
| 630 | |
| 631 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 632 | if (length > channel->max_len) |
| 633 | length = channel->max_len; |
| 634 | |
| 635 | csr = musb_readw(epio, MUSB_TXCSR); |
| 636 | if (length > pkt_size) { |
| 637 | mode = 1; |
| 638 | csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; |
| 639 | /* autoset shouldn't be set in high bandwidth */ |
| 640 | if (qh->hb_mult == 1) |
| 641 | csr |= MUSB_TXCSR_AUTOSET; |
| 642 | } else { |
| 643 | mode = 0; |
| 644 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); |
| 645 | csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ |
| 646 | } |
| 647 | channel->desired_mode = mode; |
| 648 | musb_writew(epio, MUSB_TXCSR, csr); |
| 649 | #else |
| 650 | if (!is_cppi_enabled() && !tusb_dma_omap()) |
| 651 | return false; |
| 652 | |
| 653 | channel->actual_len = 0; |
| 654 | |
| 655 | /* |
| 656 | * TX uses "RNDIS" mode automatically but needs help |
| 657 | * to identify the zero-length-final-packet case. |
| 658 | */ |
| 659 | mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; |
| 660 | #endif |
| 661 | |
| 662 | qh->segsize = length; |
| 663 | |
| 664 | /* |
| 665 | * Ensure the data reaches to main memory before starting |
| 666 | * DMA transfer |
| 667 | */ |
| 668 | wmb(); |
| 669 | |
| 670 | if (!dma->channel_program(channel, pkt_size, mode, |
| 671 | urb->transfer_dma + offset, length)) { |
| 672 | dma->channel_release(channel); |
| 673 | hw_ep->tx_channel = NULL; |
| 674 | |
| 675 | csr = musb_readw(epio, MUSB_TXCSR); |
| 676 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); |
| 677 | musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); |
| 678 | return false; |
| 679 | } |
| 680 | return true; |
| 681 | } |
| 682 | |
| 683 | /* |
| 684 | * Program an HDRC endpoint as per the given URB |
| 685 | * Context: irqs blocked, controller lock held |
| 686 | */ |
| 687 | static void musb_ep_program(struct musb *musb, u8 epnum, |
| 688 | struct urb *urb, int is_out, |
| 689 | u8 *buf, u32 offset, u32 len) |
| 690 | { |
| 691 | struct dma_controller *dma_controller; |
| 692 | struct dma_channel *dma_channel; |
| 693 | u8 dma_ok; |
| 694 | void __iomem *mbase = musb->mregs; |
| 695 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 696 | void __iomem *epio = hw_ep->regs; |
| 697 | struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); |
| 698 | u16 packet_sz = qh->maxpacket; |
| 699 | |
| 700 | dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " |
| 701 | "h_addr%02x h_port%02x bytes %d\n", |
| 702 | is_out ? "-->" : "<--", |
| 703 | epnum, urb, urb->dev->speed, |
| 704 | qh->addr_reg, qh->epnum, is_out ? "out" : "in", |
| 705 | qh->h_addr_reg, qh->h_port_reg, |
| 706 | len); |
| 707 | |
| 708 | musb_ep_select(mbase, epnum); |
| 709 | |
| 710 | /* candidate for DMA? */ |
| 711 | dma_controller = musb->dma_controller; |
| 712 | if (is_dma_capable() && epnum && dma_controller) { |
| 713 | dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; |
| 714 | if (!dma_channel) { |
| 715 | dma_channel = dma_controller->channel_alloc( |
| 716 | dma_controller, hw_ep, is_out); |
| 717 | if (is_out) |
| 718 | hw_ep->tx_channel = dma_channel; |
| 719 | else |
| 720 | hw_ep->rx_channel = dma_channel; |
| 721 | } |
| 722 | } else |
| 723 | dma_channel = NULL; |
| 724 | |
| 725 | /* make sure we clear DMAEnab, autoSet bits from previous run */ |
| 726 | |
| 727 | /* OUT/transmit/EP0 or IN/receive? */ |
| 728 | if (is_out) { |
| 729 | u16 csr; |
| 730 | u16 int_txe; |
| 731 | u16 load_count; |
| 732 | |
| 733 | csr = musb_readw(epio, MUSB_TXCSR); |
| 734 | |
| 735 | /* disable interrupt in case we flush */ |
| 736 | int_txe = musb_readw(mbase, MUSB_INTRTXE); |
| 737 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); |
| 738 | |
| 739 | /* general endpoint setup */ |
| 740 | if (epnum) { |
| 741 | /* flush all old state, set default */ |
| 742 | musb_h_tx_flush_fifo(hw_ep); |
| 743 | |
| 744 | /* |
| 745 | * We must not clear the DMAMODE bit before or in |
| 746 | * the same cycle with the DMAENAB bit, so we clear |
| 747 | * the latter first... |
| 748 | */ |
| 749 | csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT |
| 750 | | MUSB_TXCSR_AUTOSET |
| 751 | | MUSB_TXCSR_DMAENAB |
| 752 | | MUSB_TXCSR_FRCDATATOG |
| 753 | | MUSB_TXCSR_H_RXSTALL |
| 754 | | MUSB_TXCSR_H_ERROR |
| 755 | | MUSB_TXCSR_TXPKTRDY |
| 756 | ); |
| 757 | csr |= MUSB_TXCSR_MODE; |
| 758 | |
| 759 | if (usb_gettoggle(urb->dev, qh->epnum, 1)) |
| 760 | csr |= MUSB_TXCSR_H_WR_DATATOGGLE |
| 761 | | MUSB_TXCSR_H_DATATOGGLE; |
| 762 | else |
| 763 | csr |= MUSB_TXCSR_CLRDATATOG; |
| 764 | |
| 765 | musb_writew(epio, MUSB_TXCSR, csr); |
| 766 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 767 | csr &= ~MUSB_TXCSR_DMAMODE; |
| 768 | musb_writew(epio, MUSB_TXCSR, csr); |
| 769 | csr = musb_readw(epio, MUSB_TXCSR); |
| 770 | } else { |
| 771 | /* endpoint 0: just flush */ |
| 772 | musb_h_ep0_flush_fifo(hw_ep); |
| 773 | } |
| 774 | |
| 775 | /* target addr and (for multipoint) hub addr/port */ |
| 776 | if (musb->is_multipoint) { |
| 777 | musb_write_txfunaddr(mbase, epnum, qh->addr_reg); |
| 778 | musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); |
| 779 | musb_write_txhubport(mbase, epnum, qh->h_port_reg); |
| 780 | /* FIXME if !epnum, do the same for RX ... */ |
| 781 | } else |
| 782 | musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); |
| 783 | |
| 784 | /* protocol/endpoint/interval/NAKlimit */ |
| 785 | if (epnum) { |
| 786 | musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); |
| 787 | if (musb->double_buffer_not_ok) |
| 788 | musb_writew(epio, MUSB_TXMAXP, |
| 789 | hw_ep->max_packet_sz_tx); |
| 790 | else if (can_bulk_split(musb, qh->type)) |
| 791 | musb_writew(epio, MUSB_TXMAXP, packet_sz |
| 792 | | ((hw_ep->max_packet_sz_tx / |
| 793 | packet_sz) - 1) << 11); |
| 794 | else |
| 795 | musb_writew(epio, MUSB_TXMAXP, |
| 796 | qh->maxpacket | |
| 797 | ((qh->hb_mult - 1) << 11)); |
| 798 | musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); |
| 799 | } else { |
| 800 | musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); |
| 801 | if (musb->is_multipoint) |
| 802 | musb_writeb(epio, MUSB_TYPE0, |
| 803 | qh->type_reg); |
| 804 | } |
| 805 | |
| 806 | if (can_bulk_split(musb, qh->type)) |
| 807 | load_count = min((u32) hw_ep->max_packet_sz_tx, |
| 808 | len); |
| 809 | else |
| 810 | load_count = min((u32) packet_sz, len); |
| 811 | |
| 812 | if (dma_channel && musb_tx_dma_program(dma_controller, |
| 813 | hw_ep, qh, urb, offset, len)) |
| 814 | load_count = 0; |
| 815 | |
| 816 | if (load_count) { |
| 817 | /* PIO to load FIFO */ |
| 818 | qh->segsize = load_count; |
| 819 | musb_write_fifo(hw_ep, load_count, buf); |
| 820 | } |
| 821 | |
| 822 | /* re-enable interrupt */ |
| 823 | musb_writew(mbase, MUSB_INTRTXE, int_txe); |
| 824 | |
| 825 | /* IN/receive */ |
| 826 | } else { |
| 827 | u16 csr; |
| 828 | |
| 829 | if (hw_ep->rx_reinit) { |
| 830 | musb_rx_reinit(musb, qh, hw_ep); |
| 831 | |
| 832 | /* init new state: toggle and NYET, maybe DMA later */ |
| 833 | if (usb_gettoggle(urb->dev, qh->epnum, 0)) |
| 834 | csr = MUSB_RXCSR_H_WR_DATATOGGLE |
| 835 | | MUSB_RXCSR_H_DATATOGGLE; |
| 836 | else |
| 837 | csr = 0; |
| 838 | if (qh->type == USB_ENDPOINT_XFER_INT) |
| 839 | csr |= MUSB_RXCSR_DISNYET; |
| 840 | |
| 841 | } else { |
| 842 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 843 | |
| 844 | if (csr & (MUSB_RXCSR_RXPKTRDY |
| 845 | | MUSB_RXCSR_DMAENAB |
| 846 | | MUSB_RXCSR_H_REQPKT)) |
| 847 | ERR("broken !rx_reinit, ep%d csr %04x\n", |
| 848 | hw_ep->epnum, csr); |
| 849 | |
| 850 | /* scrub any stale state, leaving toggle alone */ |
| 851 | csr &= MUSB_RXCSR_DISNYET; |
| 852 | } |
| 853 | |
| 854 | /* kick things off */ |
| 855 | |
| 856 | if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { |
| 857 | /* Candidate for DMA */ |
| 858 | dma_channel->actual_len = 0L; |
| 859 | qh->segsize = len; |
| 860 | |
| 861 | /* AUTOREQ is in a DMA register */ |
| 862 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 863 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 864 | |
| 865 | /* |
| 866 | * Unless caller treats short RX transfers as |
| 867 | * errors, we dare not queue multiple transfers. |
| 868 | */ |
| 869 | dma_ok = dma_controller->channel_program(dma_channel, |
| 870 | packet_sz, !(urb->transfer_flags & |
| 871 | URB_SHORT_NOT_OK), |
| 872 | urb->transfer_dma + offset, |
| 873 | qh->segsize); |
| 874 | if (!dma_ok) { |
| 875 | dma_controller->channel_release(dma_channel); |
| 876 | hw_ep->rx_channel = dma_channel = NULL; |
| 877 | } else |
| 878 | csr |= MUSB_RXCSR_DMAENAB; |
| 879 | } |
| 880 | |
| 881 | csr |= MUSB_RXCSR_H_REQPKT; |
| 882 | dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); |
| 883 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 884 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | |
| 889 | /* |
| 890 | * Service the default endpoint (ep0) as host. |
| 891 | * Return true until it's time to start the status stage. |
| 892 | */ |
| 893 | static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) |
| 894 | { |
| 895 | bool more = false; |
| 896 | u8 *fifo_dest = NULL; |
| 897 | u16 fifo_count = 0; |
| 898 | struct musb_hw_ep *hw_ep = musb->control_ep; |
| 899 | struct musb_qh *qh = hw_ep->in_qh; |
| 900 | struct usb_ctrlrequest *request; |
| 901 | |
| 902 | switch (musb->ep0_stage) { |
| 903 | case MUSB_EP0_IN: |
| 904 | fifo_dest = urb->transfer_buffer + urb->actual_length; |
| 905 | fifo_count = min_t(size_t, len, urb->transfer_buffer_length - |
| 906 | urb->actual_length); |
| 907 | if (fifo_count < len) |
| 908 | urb->status = -EOVERFLOW; |
| 909 | |
| 910 | musb_read_fifo(hw_ep, fifo_count, fifo_dest); |
| 911 | |
| 912 | urb->actual_length += fifo_count; |
| 913 | if (len < qh->maxpacket) { |
| 914 | /* always terminate on short read; it's |
| 915 | * rarely reported as an error. |
| 916 | */ |
| 917 | } else if (urb->actual_length < |
| 918 | urb->transfer_buffer_length) |
| 919 | more = true; |
| 920 | break; |
| 921 | case MUSB_EP0_START: |
| 922 | request = (struct usb_ctrlrequest *) urb->setup_packet; |
| 923 | |
| 924 | if (!request->wLength) { |
| 925 | dev_dbg(musb->controller, "start no-DATA\n"); |
| 926 | break; |
| 927 | } else if (request->bRequestType & USB_DIR_IN) { |
| 928 | dev_dbg(musb->controller, "start IN-DATA\n"); |
| 929 | musb->ep0_stage = MUSB_EP0_IN; |
| 930 | more = true; |
| 931 | break; |
| 932 | } else { |
| 933 | dev_dbg(musb->controller, "start OUT-DATA\n"); |
| 934 | musb->ep0_stage = MUSB_EP0_OUT; |
| 935 | more = true; |
| 936 | } |
| 937 | /* FALLTHROUGH */ |
| 938 | case MUSB_EP0_OUT: |
| 939 | fifo_count = min_t(size_t, qh->maxpacket, |
| 940 | urb->transfer_buffer_length - |
| 941 | urb->actual_length); |
| 942 | if (fifo_count) { |
| 943 | fifo_dest = (u8 *) (urb->transfer_buffer |
| 944 | + urb->actual_length); |
| 945 | dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", |
| 946 | fifo_count, |
| 947 | (fifo_count == 1) ? "" : "s", |
| 948 | fifo_dest); |
| 949 | musb_write_fifo(hw_ep, fifo_count, fifo_dest); |
| 950 | |
| 951 | urb->actual_length += fifo_count; |
| 952 | more = true; |
| 953 | } |
| 954 | break; |
| 955 | default: |
| 956 | ERR("bogus ep0 stage %d\n", musb->ep0_stage); |
| 957 | break; |
| 958 | } |
| 959 | |
| 960 | return more; |
| 961 | } |
| 962 | |
| 963 | /* |
| 964 | * Handle default endpoint interrupt as host. Only called in IRQ time |
| 965 | * from musb_interrupt(). |
| 966 | * |
| 967 | * called with controller irqlocked |
| 968 | */ |
| 969 | irqreturn_t musb_h_ep0_irq(struct musb *musb) |
| 970 | { |
| 971 | struct urb *urb; |
| 972 | u16 csr, len; |
| 973 | int status = 0; |
| 974 | void __iomem *mbase = musb->mregs; |
| 975 | struct musb_hw_ep *hw_ep = musb->control_ep; |
| 976 | void __iomem *epio = hw_ep->regs; |
| 977 | struct musb_qh *qh = hw_ep->in_qh; |
| 978 | bool complete = false; |
| 979 | irqreturn_t retval = IRQ_NONE; |
| 980 | |
| 981 | /* ep0 only has one queue, "in" */ |
| 982 | urb = next_urb(qh); |
| 983 | |
| 984 | musb_ep_select(mbase, 0); |
| 985 | csr = musb_readw(epio, MUSB_CSR0); |
| 986 | len = (csr & MUSB_CSR0_RXPKTRDY) |
| 987 | ? musb_readb(epio, MUSB_COUNT0) |
| 988 | : 0; |
| 989 | |
| 990 | dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", |
| 991 | csr, qh, len, urb, musb->ep0_stage); |
| 992 | |
| 993 | /* if we just did status stage, we are done */ |
| 994 | if (MUSB_EP0_STATUS == musb->ep0_stage) { |
| 995 | retval = IRQ_HANDLED; |
| 996 | complete = true; |
| 997 | } |
| 998 | |
| 999 | /* prepare status */ |
| 1000 | if (csr & MUSB_CSR0_H_RXSTALL) { |
| 1001 | dev_dbg(musb->controller, "STALLING ENDPOINT\n"); |
| 1002 | status = -EPIPE; |
| 1003 | |
| 1004 | } else if (csr & MUSB_CSR0_H_ERROR) { |
| 1005 | dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); |
| 1006 | status = -EPROTO; |
| 1007 | |
| 1008 | } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { |
| 1009 | dev_dbg(musb->controller, "control NAK timeout\n"); |
| 1010 | |
| 1011 | /* NOTE: this code path would be a good place to PAUSE a |
| 1012 | * control transfer, if another one is queued, so that |
| 1013 | * ep0 is more likely to stay busy. That's already done |
| 1014 | * for bulk RX transfers. |
| 1015 | * |
| 1016 | * if (qh->ring.next != &musb->control), then |
| 1017 | * we have a candidate... NAKing is *NOT* an error |
| 1018 | */ |
| 1019 | musb_writew(epio, MUSB_CSR0, 0); |
| 1020 | retval = IRQ_HANDLED; |
| 1021 | } |
| 1022 | |
| 1023 | if (status) { |
| 1024 | dev_dbg(musb->controller, "aborting\n"); |
| 1025 | retval = IRQ_HANDLED; |
| 1026 | if (urb) |
| 1027 | urb->status = status; |
| 1028 | complete = true; |
| 1029 | |
| 1030 | /* use the proper sequence to abort the transfer */ |
| 1031 | if (csr & MUSB_CSR0_H_REQPKT) { |
| 1032 | csr &= ~MUSB_CSR0_H_REQPKT; |
| 1033 | musb_writew(epio, MUSB_CSR0, csr); |
| 1034 | csr &= ~MUSB_CSR0_H_NAKTIMEOUT; |
| 1035 | musb_writew(epio, MUSB_CSR0, csr); |
| 1036 | } else { |
| 1037 | musb_h_ep0_flush_fifo(hw_ep); |
| 1038 | } |
| 1039 | |
| 1040 | musb_writeb(epio, MUSB_NAKLIMIT0, 0); |
| 1041 | |
| 1042 | /* clear it */ |
| 1043 | musb_writew(epio, MUSB_CSR0, 0); |
| 1044 | } |
| 1045 | |
| 1046 | if (unlikely(!urb)) { |
| 1047 | /* stop endpoint since we have no place for its data, this |
| 1048 | * SHOULD NEVER HAPPEN! */ |
| 1049 | ERR("no URB for end 0\n"); |
| 1050 | |
| 1051 | musb_h_ep0_flush_fifo(hw_ep); |
| 1052 | goto done; |
| 1053 | } |
| 1054 | |
| 1055 | if (!complete) { |
| 1056 | /* call common logic and prepare response */ |
| 1057 | if (musb_h_ep0_continue(musb, len, urb)) { |
| 1058 | /* more packets required */ |
| 1059 | csr = (MUSB_EP0_IN == musb->ep0_stage) |
| 1060 | ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; |
| 1061 | } else { |
| 1062 | /* data transfer complete; perform status phase */ |
| 1063 | if (usb_pipeout(urb->pipe) |
| 1064 | || !urb->transfer_buffer_length) |
| 1065 | csr = MUSB_CSR0_H_STATUSPKT |
| 1066 | | MUSB_CSR0_H_REQPKT; |
| 1067 | else |
| 1068 | csr = MUSB_CSR0_H_STATUSPKT |
| 1069 | | MUSB_CSR0_TXPKTRDY; |
| 1070 | |
| 1071 | /* flag status stage */ |
| 1072 | musb->ep0_stage = MUSB_EP0_STATUS; |
| 1073 | |
| 1074 | dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); |
| 1075 | |
| 1076 | } |
| 1077 | musb_writew(epio, MUSB_CSR0, csr); |
| 1078 | retval = IRQ_HANDLED; |
| 1079 | } else |
| 1080 | musb->ep0_stage = MUSB_EP0_IDLE; |
| 1081 | |
| 1082 | /* call completion handler if done */ |
| 1083 | if (complete) |
| 1084 | musb_advance_schedule(musb, urb, hw_ep, 1); |
| 1085 | done: |
| 1086 | return retval; |
| 1087 | } |
| 1088 | |
| 1089 | |
| 1090 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1091 | |
| 1092 | /* Host side TX (OUT) using Mentor DMA works as follows: |
| 1093 | submit_urb -> |
| 1094 | - if queue was empty, Program Endpoint |
| 1095 | - ... which starts DMA to fifo in mode 1 or 0 |
| 1096 | |
| 1097 | DMA Isr (transfer complete) -> TxAvail() |
| 1098 | - Stop DMA (~DmaEnab) (<--- Alert ... currently happens |
| 1099 | only in musb_cleanup_urb) |
| 1100 | - TxPktRdy has to be set in mode 0 or for |
| 1101 | short packets in mode 1. |
| 1102 | */ |
| 1103 | |
| 1104 | #endif |
| 1105 | |
| 1106 | /* Service a Tx-Available or dma completion irq for the endpoint */ |
| 1107 | void musb_host_tx(struct musb *musb, u8 epnum) |
| 1108 | { |
| 1109 | int pipe; |
| 1110 | bool done = false; |
| 1111 | u16 tx_csr; |
| 1112 | size_t length = 0; |
| 1113 | size_t offset = 0; |
| 1114 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 1115 | void __iomem *epio = hw_ep->regs; |
| 1116 | struct musb_qh *qh = hw_ep->out_qh; |
| 1117 | struct urb *urb = next_urb(qh); |
| 1118 | u32 status = 0; |
| 1119 | void __iomem *mbase = musb->mregs; |
| 1120 | struct dma_channel *dma; |
| 1121 | bool transfer_pending = false; |
| 1122 | |
| 1123 | musb_ep_select(mbase, epnum); |
| 1124 | tx_csr = musb_readw(epio, MUSB_TXCSR); |
| 1125 | |
| 1126 | /* with CPPI, DMA sometimes triggers "extra" irqs */ |
| 1127 | if (!urb) { |
| 1128 | dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); |
| 1129 | return; |
| 1130 | } |
| 1131 | |
| 1132 | pipe = urb->pipe; |
| 1133 | dma = is_dma_capable() ? hw_ep->tx_channel : NULL; |
| 1134 | dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, |
| 1135 | dma ? ", dma" : ""); |
| 1136 | |
| 1137 | /* check for errors */ |
| 1138 | if (tx_csr & MUSB_TXCSR_H_RXSTALL) { |
| 1139 | /* dma was disabled, fifo flushed */ |
| 1140 | dev_dbg(musb->controller, "TX end %d stall\n", epnum); |
| 1141 | |
| 1142 | /* stall; record URB status */ |
| 1143 | status = -EPIPE; |
| 1144 | |
| 1145 | } else if (tx_csr & MUSB_TXCSR_H_ERROR) { |
| 1146 | /* (NON-ISO) dma was disabled, fifo flushed */ |
| 1147 | dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); |
| 1148 | |
| 1149 | status = -ETIMEDOUT; |
| 1150 | |
| 1151 | } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { |
| 1152 | dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum); |
| 1153 | |
| 1154 | /* NOTE: this code path would be a good place to PAUSE a |
| 1155 | * transfer, if there's some other (nonperiodic) tx urb |
| 1156 | * that could use this fifo. (dma complicates it...) |
| 1157 | * That's already done for bulk RX transfers. |
| 1158 | * |
| 1159 | * if (bulk && qh->ring.next != &musb->out_bulk), then |
| 1160 | * we have a candidate... NAKing is *NOT* an error |
| 1161 | */ |
| 1162 | musb_ep_select(mbase, epnum); |
| 1163 | musb_writew(epio, MUSB_TXCSR, |
| 1164 | MUSB_TXCSR_H_WZC_BITS |
| 1165 | | MUSB_TXCSR_TXPKTRDY); |
| 1166 | return; |
| 1167 | } |
| 1168 | |
| 1169 | if (status) { |
| 1170 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1171 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1172 | (void) musb->dma_controller->channel_abort(dma); |
| 1173 | } |
| 1174 | |
| 1175 | /* do the proper sequence to abort the transfer in the |
| 1176 | * usb core; the dma engine should already be stopped. |
| 1177 | */ |
| 1178 | musb_h_tx_flush_fifo(hw_ep); |
| 1179 | tx_csr &= ~(MUSB_TXCSR_AUTOSET |
| 1180 | | MUSB_TXCSR_DMAENAB |
| 1181 | | MUSB_TXCSR_H_ERROR |
| 1182 | | MUSB_TXCSR_H_RXSTALL |
| 1183 | | MUSB_TXCSR_H_NAKTIMEOUT |
| 1184 | ); |
| 1185 | |
| 1186 | musb_ep_select(mbase, epnum); |
| 1187 | musb_writew(epio, MUSB_TXCSR, tx_csr); |
| 1188 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 1189 | musb_writew(epio, MUSB_TXCSR, tx_csr); |
| 1190 | musb_writeb(epio, MUSB_TXINTERVAL, 0); |
| 1191 | |
| 1192 | done = true; |
| 1193 | } |
| 1194 | |
| 1195 | /* second cppi case */ |
| 1196 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1197 | dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); |
| 1198 | return; |
| 1199 | } |
| 1200 | |
| 1201 | if (is_dma_capable() && dma && !status) { |
| 1202 | /* |
| 1203 | * DMA has completed. But if we're using DMA mode 1 (multi |
| 1204 | * packet DMA), we need a terminal TXPKTRDY interrupt before |
| 1205 | * we can consider this transfer completed, lest we trash |
| 1206 | * its last packet when writing the next URB's data. So we |
| 1207 | * switch back to mode 0 to get that interrupt; we'll come |
| 1208 | * back here once it happens. |
| 1209 | */ |
| 1210 | if (tx_csr & MUSB_TXCSR_DMAMODE) { |
| 1211 | /* |
| 1212 | * We shouldn't clear DMAMODE with DMAENAB set; so |
| 1213 | * clear them in a safe order. That should be OK |
| 1214 | * once TXPKTRDY has been set (and I've never seen |
| 1215 | * it being 0 at this moment -- DMA interrupt latency |
| 1216 | * is significant) but if it hasn't been then we have |
| 1217 | * no choice but to stop being polite and ignore the |
| 1218 | * programmer's guide... :-) |
| 1219 | * |
| 1220 | * Note that we must write TXCSR with TXPKTRDY cleared |
| 1221 | * in order not to re-trigger the packet send (this bit |
| 1222 | * can't be cleared by CPU), and there's another caveat: |
| 1223 | * TXPKTRDY may be set shortly and then cleared in the |
| 1224 | * double-buffered FIFO mode, so we do an extra TXCSR |
| 1225 | * read for debouncing... |
| 1226 | */ |
| 1227 | tx_csr &= musb_readw(epio, MUSB_TXCSR); |
| 1228 | if (tx_csr & MUSB_TXCSR_TXPKTRDY) { |
| 1229 | tx_csr &= ~(MUSB_TXCSR_DMAENAB | |
| 1230 | MUSB_TXCSR_TXPKTRDY); |
| 1231 | musb_writew(epio, MUSB_TXCSR, |
| 1232 | tx_csr | MUSB_TXCSR_H_WZC_BITS); |
| 1233 | } |
| 1234 | tx_csr &= ~(MUSB_TXCSR_DMAMODE | |
| 1235 | MUSB_TXCSR_TXPKTRDY); |
| 1236 | musb_writew(epio, MUSB_TXCSR, |
| 1237 | tx_csr | MUSB_TXCSR_H_WZC_BITS); |
| 1238 | |
| 1239 | /* |
| 1240 | * There is no guarantee that we'll get an interrupt |
| 1241 | * after clearing DMAMODE as we might have done this |
| 1242 | * too late (after TXPKTRDY was cleared by controller). |
| 1243 | * Re-read TXCSR as we have spoiled its previous value. |
| 1244 | */ |
| 1245 | tx_csr = musb_readw(epio, MUSB_TXCSR); |
| 1246 | } |
| 1247 | |
| 1248 | /* |
| 1249 | * We may get here from a DMA completion or TXPKTRDY interrupt. |
| 1250 | * In any case, we must check the FIFO status here and bail out |
| 1251 | * only if the FIFO still has data -- that should prevent the |
| 1252 | * "missed" TXPKTRDY interrupts and deal with double-buffered |
| 1253 | * FIFO mode too... |
| 1254 | */ |
| 1255 | if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { |
| 1256 | dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " |
| 1257 | "CSR %04x\n", tx_csr); |
| 1258 | return; |
| 1259 | } |
| 1260 | } |
| 1261 | |
| 1262 | if (!status || dma || usb_pipeisoc(pipe)) { |
| 1263 | if (dma) |
| 1264 | length = dma->actual_len; |
| 1265 | else |
| 1266 | length = qh->segsize; |
| 1267 | qh->offset += length; |
| 1268 | |
| 1269 | if (usb_pipeisoc(pipe)) { |
| 1270 | #ifndef __UBOOT__ |
| 1271 | struct usb_iso_packet_descriptor *d; |
| 1272 | |
| 1273 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1274 | d->actual_length = length; |
| 1275 | d->status = status; |
| 1276 | if (++qh->iso_idx >= urb->number_of_packets) { |
| 1277 | done = true; |
| 1278 | } else { |
| 1279 | d++; |
| 1280 | offset = d->offset; |
| 1281 | length = d->length; |
| 1282 | } |
| 1283 | #endif |
| 1284 | } else if (dma && urb->transfer_buffer_length == qh->offset) { |
| 1285 | done = true; |
| 1286 | } else { |
| 1287 | /* see if we need to send more data, or ZLP */ |
| 1288 | if (qh->segsize < qh->maxpacket) |
| 1289 | done = true; |
| 1290 | else if (qh->offset == urb->transfer_buffer_length |
| 1291 | && !(urb->transfer_flags |
| 1292 | & URB_ZERO_PACKET)) |
| 1293 | done = true; |
| 1294 | if (!done) { |
| 1295 | offset = qh->offset; |
| 1296 | length = urb->transfer_buffer_length - offset; |
| 1297 | transfer_pending = true; |
| 1298 | } |
| 1299 | } |
| 1300 | } |
| 1301 | |
| 1302 | /* urb->status != -EINPROGRESS means request has been faulted, |
| 1303 | * so we must abort this transfer after cleanup |
| 1304 | */ |
| 1305 | if (urb->status != -EINPROGRESS) { |
| 1306 | done = true; |
| 1307 | if (status == 0) |
| 1308 | status = urb->status; |
| 1309 | } |
| 1310 | |
| 1311 | if (done) { |
| 1312 | /* set status */ |
| 1313 | urb->status = status; |
| 1314 | urb->actual_length = qh->offset; |
| 1315 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); |
| 1316 | return; |
| 1317 | } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { |
| 1318 | if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, |
| 1319 | offset, length)) { |
| 1320 | if (is_cppi_enabled() || tusb_dma_omap()) |
| 1321 | musb_h_tx_dma_start(hw_ep); |
| 1322 | return; |
| 1323 | } |
| 1324 | } else if (tx_csr & MUSB_TXCSR_DMAENAB) { |
| 1325 | dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); |
| 1326 | return; |
| 1327 | } |
| 1328 | |
| 1329 | /* |
| 1330 | * PIO: start next packet in this URB. |
| 1331 | * |
| 1332 | * REVISIT: some docs say that when hw_ep->tx_double_buffered, |
| 1333 | * (and presumably, FIFO is not half-full) we should write *two* |
| 1334 | * packets before updating TXCSR; other docs disagree... |
| 1335 | */ |
| 1336 | if (length > qh->maxpacket) |
| 1337 | length = qh->maxpacket; |
| 1338 | /* Unmap the buffer so that CPU can use it */ |
| 1339 | usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); |
| 1340 | musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); |
| 1341 | qh->segsize = length; |
| 1342 | |
| 1343 | musb_ep_select(mbase, epnum); |
| 1344 | musb_writew(epio, MUSB_TXCSR, |
| 1345 | MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); |
| 1346 | } |
| 1347 | |
| 1348 | |
| 1349 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1350 | |
| 1351 | /* Host side RX (IN) using Mentor DMA works as follows: |
| 1352 | submit_urb -> |
| 1353 | - if queue was empty, ProgramEndpoint |
| 1354 | - first IN token is sent out (by setting ReqPkt) |
| 1355 | LinuxIsr -> RxReady() |
| 1356 | /\ => first packet is received |
| 1357 | | - Set in mode 0 (DmaEnab, ~ReqPkt) |
| 1358 | | -> DMA Isr (transfer complete) -> RxReady() |
| 1359 | | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) |
| 1360 | | - if urb not complete, send next IN token (ReqPkt) |
| 1361 | | | else complete urb. |
| 1362 | | | |
| 1363 | --------------------------- |
| 1364 | * |
| 1365 | * Nuances of mode 1: |
| 1366 | * For short packets, no ack (+RxPktRdy) is sent automatically |
| 1367 | * (even if AutoClear is ON) |
| 1368 | * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent |
| 1369 | * automatically => major problem, as collecting the next packet becomes |
| 1370 | * difficult. Hence mode 1 is not used. |
| 1371 | * |
| 1372 | * REVISIT |
| 1373 | * All we care about at this driver level is that |
| 1374 | * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; |
| 1375 | * (b) termination conditions are: short RX, or buffer full; |
| 1376 | * (c) fault modes include |
| 1377 | * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. |
| 1378 | * (and that endpoint's dma queue stops immediately) |
| 1379 | * - overflow (full, PLUS more bytes in the terminal packet) |
| 1380 | * |
| 1381 | * So for example, usb-storage sets URB_SHORT_NOT_OK, and would |
| 1382 | * thus be a great candidate for using mode 1 ... for all but the |
| 1383 | * last packet of one URB's transfer. |
| 1384 | */ |
| 1385 | |
| 1386 | #endif |
| 1387 | |
| 1388 | /* Schedule next QH from musb->in_bulk and move the current qh to |
| 1389 | * the end; avoids starvation for other endpoints. |
| 1390 | */ |
| 1391 | static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) |
| 1392 | { |
| 1393 | struct dma_channel *dma; |
| 1394 | struct urb *urb; |
| 1395 | void __iomem *mbase = musb->mregs; |
| 1396 | void __iomem *epio = ep->regs; |
| 1397 | struct musb_qh *cur_qh, *next_qh; |
| 1398 | u16 rx_csr; |
| 1399 | |
| 1400 | musb_ep_select(mbase, ep->epnum); |
| 1401 | dma = is_dma_capable() ? ep->rx_channel : NULL; |
| 1402 | |
| 1403 | /* clear nak timeout bit */ |
| 1404 | rx_csr = musb_readw(epio, MUSB_RXCSR); |
| 1405 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; |
| 1406 | rx_csr &= ~MUSB_RXCSR_DATAERROR; |
| 1407 | musb_writew(epio, MUSB_RXCSR, rx_csr); |
| 1408 | |
| 1409 | cur_qh = first_qh(&musb->in_bulk); |
| 1410 | if (cur_qh) { |
| 1411 | urb = next_urb(cur_qh); |
| 1412 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1413 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1414 | musb->dma_controller->channel_abort(dma); |
| 1415 | urb->actual_length += dma->actual_len; |
| 1416 | dma->actual_len = 0L; |
| 1417 | } |
| 1418 | musb_save_toggle(cur_qh, 1, urb); |
| 1419 | |
| 1420 | /* move cur_qh to end of queue */ |
| 1421 | list_move_tail(&cur_qh->ring, &musb->in_bulk); |
| 1422 | |
| 1423 | /* get the next qh from musb->in_bulk */ |
| 1424 | next_qh = first_qh(&musb->in_bulk); |
| 1425 | |
| 1426 | /* set rx_reinit and schedule the next qh */ |
| 1427 | ep->rx_reinit = 1; |
| 1428 | musb_start_urb(musb, 1, next_qh); |
| 1429 | } |
| 1430 | } |
| 1431 | |
| 1432 | /* |
| 1433 | * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, |
| 1434 | * and high-bandwidth IN transfer cases. |
| 1435 | */ |
| 1436 | void musb_host_rx(struct musb *musb, u8 epnum) |
| 1437 | { |
| 1438 | struct urb *urb; |
| 1439 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 1440 | void __iomem *epio = hw_ep->regs; |
| 1441 | struct musb_qh *qh = hw_ep->in_qh; |
| 1442 | size_t xfer_len; |
| 1443 | void __iomem *mbase = musb->mregs; |
| 1444 | int pipe; |
| 1445 | u16 rx_csr, val; |
| 1446 | bool iso_err = false; |
| 1447 | bool done = false; |
| 1448 | u32 status; |
| 1449 | struct dma_channel *dma; |
| 1450 | |
| 1451 | musb_ep_select(mbase, epnum); |
| 1452 | |
| 1453 | urb = next_urb(qh); |
| 1454 | dma = is_dma_capable() ? hw_ep->rx_channel : NULL; |
| 1455 | status = 0; |
| 1456 | xfer_len = 0; |
| 1457 | |
| 1458 | rx_csr = musb_readw(epio, MUSB_RXCSR); |
| 1459 | val = rx_csr; |
| 1460 | |
| 1461 | if (unlikely(!urb)) { |
| 1462 | /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least |
| 1463 | * usbtest #11 (unlinks) triggers it regularly, sometimes |
| 1464 | * with fifo full. (Only with DMA??) |
| 1465 | */ |
| 1466 | dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, |
| 1467 | musb_readw(epio, MUSB_RXCOUNT)); |
| 1468 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); |
| 1469 | return; |
| 1470 | } |
| 1471 | |
| 1472 | pipe = urb->pipe; |
| 1473 | |
| 1474 | dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", |
| 1475 | epnum, rx_csr, urb->actual_length, |
| 1476 | dma ? dma->actual_len : 0); |
| 1477 | |
| 1478 | /* check for errors, concurrent stall & unlink is not really |
| 1479 | * handled yet! */ |
| 1480 | if (rx_csr & MUSB_RXCSR_H_RXSTALL) { |
| 1481 | dev_dbg(musb->controller, "RX end %d STALL\n", epnum); |
| 1482 | |
| 1483 | /* stall; record URB status */ |
| 1484 | status = -EPIPE; |
| 1485 | |
| 1486 | } else if (rx_csr & MUSB_RXCSR_H_ERROR) { |
| 1487 | dev_dbg(musb->controller, "end %d RX proto error\n", epnum); |
| 1488 | |
| 1489 | status = -EPROTO; |
| 1490 | musb_writeb(epio, MUSB_RXINTERVAL, 0); |
| 1491 | |
| 1492 | } else if (rx_csr & MUSB_RXCSR_DATAERROR) { |
| 1493 | |
| 1494 | if (USB_ENDPOINT_XFER_ISOC != qh->type) { |
| 1495 | dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); |
| 1496 | |
| 1497 | /* NOTE: NAKing is *NOT* an error, so we want to |
| 1498 | * continue. Except ... if there's a request for |
| 1499 | * another QH, use that instead of starving it. |
| 1500 | * |
| 1501 | * Devices like Ethernet and serial adapters keep |
| 1502 | * reads posted at all times, which will starve |
| 1503 | * other devices without this logic. |
| 1504 | */ |
| 1505 | if (usb_pipebulk(urb->pipe) |
| 1506 | && qh->mux == 1 |
| 1507 | && !list_is_singular(&musb->in_bulk)) { |
| 1508 | musb_bulk_rx_nak_timeout(musb, hw_ep); |
| 1509 | return; |
| 1510 | } |
| 1511 | musb_ep_select(mbase, epnum); |
| 1512 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; |
| 1513 | rx_csr &= ~MUSB_RXCSR_DATAERROR; |
| 1514 | musb_writew(epio, MUSB_RXCSR, rx_csr); |
| 1515 | |
| 1516 | goto finish; |
| 1517 | } else { |
| 1518 | dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); |
| 1519 | /* packet error reported later */ |
| 1520 | iso_err = true; |
| 1521 | } |
| 1522 | } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { |
| 1523 | dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", |
| 1524 | epnum); |
| 1525 | status = -EPROTO; |
| 1526 | } |
| 1527 | |
| 1528 | /* faults abort the transfer */ |
| 1529 | if (status) { |
| 1530 | /* clean up dma and collect transfer count */ |
| 1531 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1532 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1533 | (void) musb->dma_controller->channel_abort(dma); |
| 1534 | xfer_len = dma->actual_len; |
| 1535 | } |
| 1536 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); |
| 1537 | musb_writeb(epio, MUSB_RXINTERVAL, 0); |
| 1538 | done = true; |
| 1539 | goto finish; |
| 1540 | } |
| 1541 | |
| 1542 | if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { |
| 1543 | /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ |
| 1544 | ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); |
| 1545 | goto finish; |
| 1546 | } |
| 1547 | |
| 1548 | /* thorough shutdown for now ... given more precise fault handling |
| 1549 | * and better queueing support, we might keep a DMA pipeline going |
| 1550 | * while processing this irq for earlier completions. |
| 1551 | */ |
| 1552 | |
| 1553 | /* FIXME this is _way_ too much in-line logic for Mentor DMA */ |
| 1554 | |
| 1555 | #ifndef CONFIG_USB_INVENTRA_DMA |
| 1556 | if (rx_csr & MUSB_RXCSR_H_REQPKT) { |
| 1557 | /* REVISIT this happened for a while on some short reads... |
| 1558 | * the cleanup still needs investigation... looks bad... |
| 1559 | * and also duplicates dma cleanup code above ... plus, |
| 1560 | * shouldn't this be the "half full" double buffer case? |
| 1561 | */ |
| 1562 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1563 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1564 | (void) musb->dma_controller->channel_abort(dma); |
| 1565 | xfer_len = dma->actual_len; |
| 1566 | done = true; |
| 1567 | } |
| 1568 | |
| 1569 | dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, |
| 1570 | xfer_len, dma ? ", dma" : ""); |
| 1571 | rx_csr &= ~MUSB_RXCSR_H_REQPKT; |
| 1572 | |
| 1573 | musb_ep_select(mbase, epnum); |
| 1574 | musb_writew(epio, MUSB_RXCSR, |
| 1575 | MUSB_RXCSR_H_WZC_BITS | rx_csr); |
| 1576 | } |
| 1577 | #endif |
| 1578 | if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { |
| 1579 | xfer_len = dma->actual_len; |
| 1580 | |
| 1581 | val &= ~(MUSB_RXCSR_DMAENAB |
| 1582 | | MUSB_RXCSR_H_AUTOREQ |
| 1583 | | MUSB_RXCSR_AUTOCLEAR |
| 1584 | | MUSB_RXCSR_RXPKTRDY); |
| 1585 | musb_writew(hw_ep->regs, MUSB_RXCSR, val); |
| 1586 | |
| 1587 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1588 | if (usb_pipeisoc(pipe)) { |
| 1589 | struct usb_iso_packet_descriptor *d; |
| 1590 | |
| 1591 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1592 | d->actual_length = xfer_len; |
| 1593 | |
| 1594 | /* even if there was an error, we did the dma |
| 1595 | * for iso_frame_desc->length |
| 1596 | */ |
| 1597 | if (d->status != -EILSEQ && d->status != -EOVERFLOW) |
| 1598 | d->status = 0; |
| 1599 | |
| 1600 | if (++qh->iso_idx >= urb->number_of_packets) |
| 1601 | done = true; |
| 1602 | else |
| 1603 | done = false; |
| 1604 | |
| 1605 | } else { |
| 1606 | /* done if urb buffer is full or short packet is recd */ |
| 1607 | done = (urb->actual_length + xfer_len >= |
| 1608 | urb->transfer_buffer_length |
| 1609 | || dma->actual_len < qh->maxpacket); |
| 1610 | } |
| 1611 | |
| 1612 | /* send IN token for next packet, without AUTOREQ */ |
| 1613 | if (!done) { |
| 1614 | val |= MUSB_RXCSR_H_REQPKT; |
| 1615 | musb_writew(epio, MUSB_RXCSR, |
| 1616 | MUSB_RXCSR_H_WZC_BITS | val); |
| 1617 | } |
| 1618 | |
| 1619 | dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, |
| 1620 | done ? "off" : "reset", |
| 1621 | musb_readw(epio, MUSB_RXCSR), |
| 1622 | musb_readw(epio, MUSB_RXCOUNT)); |
| 1623 | #else |
| 1624 | done = true; |
| 1625 | #endif |
| 1626 | } else if (urb->status == -EINPROGRESS) { |
| 1627 | /* if no errors, be sure a packet is ready for unloading */ |
| 1628 | if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { |
| 1629 | status = -EPROTO; |
| 1630 | ERR("Rx interrupt with no errors or packet!\n"); |
| 1631 | |
| 1632 | /* FIXME this is another "SHOULD NEVER HAPPEN" */ |
| 1633 | |
| 1634 | /* SCRUB (RX) */ |
| 1635 | /* do the proper sequence to abort the transfer */ |
| 1636 | musb_ep_select(mbase, epnum); |
| 1637 | val &= ~MUSB_RXCSR_H_REQPKT; |
| 1638 | musb_writew(epio, MUSB_RXCSR, val); |
| 1639 | goto finish; |
| 1640 | } |
| 1641 | |
| 1642 | /* we are expecting IN packets */ |
| 1643 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1644 | if (dma) { |
| 1645 | struct dma_controller *c; |
| 1646 | u16 rx_count; |
| 1647 | int ret, length; |
| 1648 | dma_addr_t buf; |
| 1649 | |
| 1650 | rx_count = musb_readw(epio, MUSB_RXCOUNT); |
| 1651 | |
| 1652 | dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n", |
| 1653 | epnum, rx_count, |
| 1654 | urb->transfer_dma |
| 1655 | + urb->actual_length, |
| 1656 | qh->offset, |
| 1657 | urb->transfer_buffer_length); |
| 1658 | |
| 1659 | c = musb->dma_controller; |
| 1660 | |
| 1661 | if (usb_pipeisoc(pipe)) { |
| 1662 | int d_status = 0; |
| 1663 | struct usb_iso_packet_descriptor *d; |
| 1664 | |
| 1665 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1666 | |
| 1667 | if (iso_err) { |
| 1668 | d_status = -EILSEQ; |
| 1669 | urb->error_count++; |
| 1670 | } |
| 1671 | if (rx_count > d->length) { |
| 1672 | if (d_status == 0) { |
| 1673 | d_status = -EOVERFLOW; |
| 1674 | urb->error_count++; |
| 1675 | } |
| 1676 | dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\ |
| 1677 | rx_count, d->length); |
| 1678 | |
| 1679 | length = d->length; |
| 1680 | } else |
| 1681 | length = rx_count; |
| 1682 | d->status = d_status; |
| 1683 | buf = urb->transfer_dma + d->offset; |
| 1684 | } else { |
| 1685 | length = rx_count; |
| 1686 | buf = urb->transfer_dma + |
| 1687 | urb->actual_length; |
| 1688 | } |
| 1689 | |
| 1690 | dma->desired_mode = 0; |
| 1691 | #ifdef USE_MODE1 |
| 1692 | /* because of the issue below, mode 1 will |
| 1693 | * only rarely behave with correct semantics. |
| 1694 | */ |
| 1695 | if ((urb->transfer_flags & |
| 1696 | URB_SHORT_NOT_OK) |
| 1697 | && (urb->transfer_buffer_length - |
| 1698 | urb->actual_length) |
| 1699 | > qh->maxpacket) |
| 1700 | dma->desired_mode = 1; |
| 1701 | if (rx_count < hw_ep->max_packet_sz_rx) { |
| 1702 | length = rx_count; |
| 1703 | dma->desired_mode = 0; |
| 1704 | } else { |
| 1705 | length = urb->transfer_buffer_length; |
| 1706 | } |
| 1707 | #endif |
| 1708 | |
| 1709 | /* Disadvantage of using mode 1: |
| 1710 | * It's basically usable only for mass storage class; essentially all |
| 1711 | * other protocols also terminate transfers on short packets. |
| 1712 | * |
| 1713 | * Details: |
| 1714 | * An extra IN token is sent at the end of the transfer (due to AUTOREQ) |
| 1715 | * If you try to use mode 1 for (transfer_buffer_length - 512), and try |
| 1716 | * to use the extra IN token to grab the last packet using mode 0, then |
| 1717 | * the problem is that you cannot be sure when the device will send the |
| 1718 | * last packet and RxPktRdy set. Sometimes the packet is recd too soon |
| 1719 | * such that it gets lost when RxCSR is re-set at the end of the mode 1 |
| 1720 | * transfer, while sometimes it is recd just a little late so that if you |
| 1721 | * try to configure for mode 0 soon after the mode 1 transfer is |
| 1722 | * completed, you will find rxcount 0. Okay, so you might think why not |
| 1723 | * wait for an interrupt when the pkt is recd. Well, you won't get any! |
| 1724 | */ |
| 1725 | |
| 1726 | val = musb_readw(epio, MUSB_RXCSR); |
| 1727 | val &= ~MUSB_RXCSR_H_REQPKT; |
| 1728 | |
| 1729 | if (dma->desired_mode == 0) |
| 1730 | val &= ~MUSB_RXCSR_H_AUTOREQ; |
| 1731 | else |
| 1732 | val |= MUSB_RXCSR_H_AUTOREQ; |
| 1733 | val |= MUSB_RXCSR_DMAENAB; |
| 1734 | |
| 1735 | /* autoclear shouldn't be set in high bandwidth */ |
| 1736 | if (qh->hb_mult == 1) |
| 1737 | val |= MUSB_RXCSR_AUTOCLEAR; |
| 1738 | |
| 1739 | musb_writew(epio, MUSB_RXCSR, |
| 1740 | MUSB_RXCSR_H_WZC_BITS | val); |
| 1741 | |
| 1742 | /* REVISIT if when actual_length != 0, |
| 1743 | * transfer_buffer_length needs to be |
| 1744 | * adjusted first... |
| 1745 | */ |
| 1746 | ret = c->channel_program( |
| 1747 | dma, qh->maxpacket, |
| 1748 | dma->desired_mode, buf, length); |
| 1749 | |
| 1750 | if (!ret) { |
| 1751 | c->channel_release(dma); |
| 1752 | hw_ep->rx_channel = NULL; |
| 1753 | dma = NULL; |
| 1754 | val = musb_readw(epio, MUSB_RXCSR); |
| 1755 | val &= ~(MUSB_RXCSR_DMAENAB |
| 1756 | | MUSB_RXCSR_H_AUTOREQ |
| 1757 | | MUSB_RXCSR_AUTOCLEAR); |
| 1758 | musb_writew(epio, MUSB_RXCSR, val); |
| 1759 | } |
| 1760 | } |
| 1761 | #endif /* Mentor DMA */ |
| 1762 | |
| 1763 | if (!dma) { |
| 1764 | /* Unmap the buffer so that CPU can use it */ |
| 1765 | usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); |
| 1766 | done = musb_host_packet_rx(musb, urb, |
| 1767 | epnum, iso_err); |
| 1768 | dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); |
| 1769 | } |
| 1770 | } |
| 1771 | |
| 1772 | finish: |
| 1773 | urb->actual_length += xfer_len; |
| 1774 | qh->offset += xfer_len; |
| 1775 | if (done) { |
| 1776 | if (urb->status == -EINPROGRESS) |
| 1777 | urb->status = status; |
| 1778 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); |
| 1779 | } |
| 1780 | } |
| 1781 | |
| 1782 | /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. |
| 1783 | * the software schedule associates multiple such nodes with a given |
| 1784 | * host side hardware endpoint + direction; scheduling may activate |
| 1785 | * that hardware endpoint. |
| 1786 | */ |
| 1787 | static int musb_schedule( |
| 1788 | struct musb *musb, |
| 1789 | struct musb_qh *qh, |
| 1790 | int is_in) |
| 1791 | { |
| 1792 | int idle; |
| 1793 | int best_diff; |
| 1794 | int best_end, epnum; |
| 1795 | struct musb_hw_ep *hw_ep = NULL; |
| 1796 | struct list_head *head = NULL; |
| 1797 | u8 toggle; |
| 1798 | u8 txtype; |
| 1799 | struct urb *urb = next_urb(qh); |
| 1800 | |
| 1801 | /* use fixed hardware for control and bulk */ |
| 1802 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { |
| 1803 | head = &musb->control; |
| 1804 | hw_ep = musb->control_ep; |
| 1805 | goto success; |
| 1806 | } |
| 1807 | |
| 1808 | /* else, periodic transfers get muxed to other endpoints */ |
| 1809 | |
| 1810 | /* |
| 1811 | * We know this qh hasn't been scheduled, so all we need to do |
| 1812 | * is choose which hardware endpoint to put it on ... |
| 1813 | * |
| 1814 | * REVISIT what we really want here is a regular schedule tree |
| 1815 | * like e.g. OHCI uses. |
| 1816 | */ |
| 1817 | best_diff = 4096; |
| 1818 | best_end = -1; |
| 1819 | |
| 1820 | for (epnum = 1, hw_ep = musb->endpoints + 1; |
| 1821 | epnum < musb->nr_endpoints; |
| 1822 | epnum++, hw_ep++) { |
| 1823 | int diff; |
| 1824 | |
| 1825 | if (musb_ep_get_qh(hw_ep, is_in) != NULL) |
| 1826 | continue; |
| 1827 | |
| 1828 | if (hw_ep == musb->bulk_ep) |
| 1829 | continue; |
| 1830 | |
| 1831 | if (is_in) |
| 1832 | diff = hw_ep->max_packet_sz_rx; |
| 1833 | else |
| 1834 | diff = hw_ep->max_packet_sz_tx; |
| 1835 | diff -= (qh->maxpacket * qh->hb_mult); |
| 1836 | |
| 1837 | if (diff >= 0 && best_diff > diff) { |
| 1838 | |
| 1839 | /* |
| 1840 | * Mentor controller has a bug in that if we schedule |
| 1841 | * a BULK Tx transfer on an endpoint that had earlier |
| 1842 | * handled ISOC then the BULK transfer has to start on |
| 1843 | * a zero toggle. If the BULK transfer starts on a 1 |
| 1844 | * toggle then this transfer will fail as the mentor |
| 1845 | * controller starts the Bulk transfer on a 0 toggle |
| 1846 | * irrespective of the programming of the toggle bits |
| 1847 | * in the TXCSR register. Check for this condition |
| 1848 | * while allocating the EP for a Tx Bulk transfer. If |
| 1849 | * so skip this EP. |
| 1850 | */ |
| 1851 | hw_ep = musb->endpoints + epnum; |
| 1852 | toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); |
| 1853 | txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) |
| 1854 | >> 4) & 0x3; |
| 1855 | if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && |
| 1856 | toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) |
| 1857 | continue; |
| 1858 | |
| 1859 | best_diff = diff; |
| 1860 | best_end = epnum; |
| 1861 | } |
| 1862 | } |
| 1863 | /* use bulk reserved ep1 if no other ep is free */ |
| 1864 | if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { |
| 1865 | hw_ep = musb->bulk_ep; |
| 1866 | if (is_in) |
| 1867 | head = &musb->in_bulk; |
| 1868 | else |
| 1869 | head = &musb->out_bulk; |
| 1870 | |
| 1871 | /* Enable bulk RX NAK timeout scheme when bulk requests are |
| 1872 | * multiplexed. This scheme doen't work in high speed to full |
| 1873 | * speed scenario as NAK interrupts are not coming from a |
| 1874 | * full speed device connected to a high speed device. |
| 1875 | * NAK timeout interval is 8 (128 uframe or 16ms) for HS and |
| 1876 | * 4 (8 frame or 8ms) for FS device. |
| 1877 | */ |
| 1878 | if (is_in && qh->dev) |
| 1879 | qh->intv_reg = |
| 1880 | (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; |
| 1881 | goto success; |
| 1882 | } else if (best_end < 0) { |
| 1883 | return -ENOSPC; |
| 1884 | } |
| 1885 | |
| 1886 | idle = 1; |
| 1887 | qh->mux = 0; |
| 1888 | hw_ep = musb->endpoints + best_end; |
| 1889 | dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); |
| 1890 | success: |
| 1891 | if (head) { |
| 1892 | idle = list_empty(head); |
| 1893 | list_add_tail(&qh->ring, head); |
| 1894 | qh->mux = 1; |
| 1895 | } |
| 1896 | qh->hw_ep = hw_ep; |
| 1897 | qh->hep->hcpriv = qh; |
| 1898 | if (idle) |
| 1899 | musb_start_urb(musb, is_in, qh); |
| 1900 | return 0; |
| 1901 | } |
| 1902 | |
| 1903 | #ifdef __UBOOT__ |
| 1904 | /* check if transaction translator is needed for device */ |
| 1905 | static int tt_needed(struct musb *musb, struct usb_device *dev) |
| 1906 | { |
| 1907 | if ((musb_readb(musb->mregs, MUSB_POWER) & MUSB_POWER_HSMODE) && |
| 1908 | (dev->speed < USB_SPEED_HIGH)) |
| 1909 | return 1; |
| 1910 | return 0; |
| 1911 | } |
| 1912 | #endif |
| 1913 | |
| 1914 | #ifndef __UBOOT__ |
| 1915 | static int musb_urb_enqueue( |
| 1916 | #else |
| 1917 | int musb_urb_enqueue( |
| 1918 | #endif |
| 1919 | struct usb_hcd *hcd, |
| 1920 | struct urb *urb, |
| 1921 | gfp_t mem_flags) |
| 1922 | { |
| 1923 | unsigned long flags; |
| 1924 | struct musb *musb = hcd_to_musb(hcd); |
| 1925 | struct usb_host_endpoint *hep = urb->ep; |
| 1926 | struct musb_qh *qh; |
| 1927 | struct usb_endpoint_descriptor *epd = &hep->desc; |
| 1928 | int ret; |
| 1929 | unsigned type_reg; |
| 1930 | unsigned interval; |
| 1931 | |
| 1932 | /* host role must be active */ |
| 1933 | if (!is_host_active(musb) || !musb->is_active) |
| 1934 | return -ENODEV; |
| 1935 | |
| 1936 | spin_lock_irqsave(&musb->lock, flags); |
| 1937 | ret = usb_hcd_link_urb_to_ep(hcd, urb); |
| 1938 | qh = ret ? NULL : hep->hcpriv; |
| 1939 | if (qh) |
| 1940 | urb->hcpriv = qh; |
| 1941 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1942 | |
| 1943 | /* DMA mapping was already done, if needed, and this urb is on |
| 1944 | * hep->urb_list now ... so we're done, unless hep wasn't yet |
| 1945 | * scheduled onto a live qh. |
| 1946 | * |
| 1947 | * REVISIT best to keep hep->hcpriv valid until the endpoint gets |
| 1948 | * disabled, testing for empty qh->ring and avoiding qh setup costs |
| 1949 | * except for the first urb queued after a config change. |
| 1950 | */ |
| 1951 | if (qh || ret) |
| 1952 | return ret; |
| 1953 | |
| 1954 | /* Allocate and initialize qh, minimizing the work done each time |
| 1955 | * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. |
| 1956 | * |
| 1957 | * REVISIT consider a dedicated qh kmem_cache, so it's harder |
| 1958 | * for bugs in other kernel code to break this driver... |
| 1959 | */ |
| 1960 | qh = kzalloc(sizeof *qh, mem_flags); |
| 1961 | if (!qh) { |
| 1962 | spin_lock_irqsave(&musb->lock, flags); |
| 1963 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 1964 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1965 | return -ENOMEM; |
| 1966 | } |
| 1967 | |
| 1968 | qh->hep = hep; |
| 1969 | qh->dev = urb->dev; |
| 1970 | INIT_LIST_HEAD(&qh->ring); |
| 1971 | qh->is_ready = 1; |
| 1972 | |
| 1973 | qh->maxpacket = usb_endpoint_maxp(epd); |
| 1974 | qh->type = usb_endpoint_type(epd); |
| 1975 | |
| 1976 | /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. |
| 1977 | * Some musb cores don't support high bandwidth ISO transfers; and |
| 1978 | * we don't (yet!) support high bandwidth interrupt transfers. |
| 1979 | */ |
| 1980 | qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); |
| 1981 | if (qh->hb_mult > 1) { |
| 1982 | int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); |
| 1983 | |
| 1984 | if (ok) |
| 1985 | ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) |
| 1986 | || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); |
| 1987 | if (!ok) { |
| 1988 | ret = -EMSGSIZE; |
| 1989 | goto done; |
| 1990 | } |
| 1991 | qh->maxpacket &= 0x7ff; |
| 1992 | } |
| 1993 | |
| 1994 | qh->epnum = usb_endpoint_num(epd); |
| 1995 | |
| 1996 | /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ |
| 1997 | qh->addr_reg = (u8) usb_pipedevice(urb->pipe); |
| 1998 | |
| 1999 | /* precompute rxtype/txtype/type0 register */ |
| 2000 | type_reg = (qh->type << 4) | qh->epnum; |
| 2001 | switch (urb->dev->speed) { |
| 2002 | case USB_SPEED_LOW: |
| 2003 | type_reg |= 0xc0; |
| 2004 | break; |
| 2005 | case USB_SPEED_FULL: |
| 2006 | type_reg |= 0x80; |
| 2007 | break; |
| 2008 | default: |
| 2009 | type_reg |= 0x40; |
| 2010 | } |
| 2011 | qh->type_reg = type_reg; |
| 2012 | |
| 2013 | /* Precompute RXINTERVAL/TXINTERVAL register */ |
| 2014 | switch (qh->type) { |
| 2015 | case USB_ENDPOINT_XFER_INT: |
| 2016 | /* |
| 2017 | * Full/low speeds use the linear encoding, |
| 2018 | * high speed uses the logarithmic encoding. |
| 2019 | */ |
| 2020 | if (urb->dev->speed <= USB_SPEED_FULL) { |
| 2021 | interval = max_t(u8, epd->bInterval, 1); |
| 2022 | break; |
| 2023 | } |
| 2024 | /* FALLTHROUGH */ |
| 2025 | case USB_ENDPOINT_XFER_ISOC: |
| 2026 | /* ISO always uses logarithmic encoding */ |
| 2027 | interval = min_t(u8, epd->bInterval, 16); |
| 2028 | break; |
| 2029 | default: |
| 2030 | /* REVISIT we actually want to use NAK limits, hinting to the |
| 2031 | * transfer scheduling logic to try some other qh, e.g. try |
| 2032 | * for 2 msec first: |
| 2033 | * |
| 2034 | * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; |
| 2035 | * |
| 2036 | * The downside of disabling this is that transfer scheduling |
| 2037 | * gets VERY unfair for nonperiodic transfers; a misbehaving |
| 2038 | * peripheral could make that hurt. That's perfectly normal |
| 2039 | * for reads from network or serial adapters ... so we have |
| 2040 | * partial NAKlimit support for bulk RX. |
| 2041 | * |
| 2042 | * The upside of disabling it is simpler transfer scheduling. |
| 2043 | */ |
| 2044 | interval = 0; |
| 2045 | } |
| 2046 | qh->intv_reg = interval; |
| 2047 | |
| 2048 | /* precompute addressing for external hub/tt ports */ |
| 2049 | if (musb->is_multipoint) { |
Hans de Goede | 4d8b8df | 2015-06-17 21:33:55 +0200 | [diff] [blame] | 2050 | #ifndef __UBOOT__ |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 2051 | struct usb_device *parent = urb->dev->parent; |
Hans de Goede | 4d8b8df | 2015-06-17 21:33:55 +0200 | [diff] [blame] | 2052 | #else |
| 2053 | struct usb_device *parent = usb_dev_get_parent(urb->dev); |
| 2054 | #endif |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 2055 | |
| 2056 | #ifndef __UBOOT__ |
| 2057 | if (parent != hcd->self.root_hub) { |
| 2058 | #else |
| 2059 | if (parent) { |
| 2060 | #endif |
| 2061 | qh->h_addr_reg = (u8) parent->devnum; |
| 2062 | |
| 2063 | #ifndef __UBOOT__ |
| 2064 | /* set up tt info if needed */ |
| 2065 | if (urb->dev->tt) { |
| 2066 | qh->h_port_reg = (u8) urb->dev->ttport; |
| 2067 | if (urb->dev->tt->hub) |
| 2068 | qh->h_addr_reg = |
| 2069 | (u8) urb->dev->tt->hub->devnum; |
| 2070 | if (urb->dev->tt->multi) |
| 2071 | qh->h_addr_reg |= 0x80; |
| 2072 | } |
| 2073 | #else |
| 2074 | if (tt_needed(musb, urb->dev)) { |
Stefan Brüns | a010568 | 2015-12-22 01:21:03 +0100 | [diff] [blame] | 2075 | uint8_t portnr = 0; |
| 2076 | uint8_t hubaddr = 0; |
| 2077 | usb_find_usb2_hub_address_port(urb->dev, |
| 2078 | &hubaddr, |
| 2079 | &portnr); |
| 2080 | qh->h_addr_reg = hubaddr; |
Stefan Brüns | 8f53bf0 | 2015-12-22 01:21:04 +0100 | [diff] [blame] | 2081 | qh->h_port_reg = portnr; |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 2082 | } |
| 2083 | #endif |
| 2084 | } |
| 2085 | } |
| 2086 | |
| 2087 | /* invariant: hep->hcpriv is null OR the qh that's already scheduled. |
| 2088 | * until we get real dma queues (with an entry for each urb/buffer), |
| 2089 | * we only have work to do in the former case. |
| 2090 | */ |
| 2091 | spin_lock_irqsave(&musb->lock, flags); |
| 2092 | if (hep->hcpriv) { |
| 2093 | /* some concurrent activity submitted another urb to hep... |
| 2094 | * odd, rare, error prone, but legal. |
| 2095 | */ |
| 2096 | kfree(qh); |
| 2097 | qh = NULL; |
| 2098 | ret = 0; |
| 2099 | } else |
| 2100 | ret = musb_schedule(musb, qh, |
| 2101 | epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); |
| 2102 | |
| 2103 | if (ret == 0) { |
| 2104 | urb->hcpriv = qh; |
| 2105 | /* FIXME set urb->start_frame for iso/intr, it's tested in |
| 2106 | * musb_start_urb(), but otherwise only konicawc cares ... |
| 2107 | */ |
| 2108 | } |
| 2109 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2110 | |
| 2111 | done: |
| 2112 | if (ret != 0) { |
| 2113 | spin_lock_irqsave(&musb->lock, flags); |
| 2114 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 2115 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2116 | kfree(qh); |
| 2117 | } |
| 2118 | return ret; |
| 2119 | } |
| 2120 | |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 2121 | /* |
| 2122 | * abort a transfer that's at the head of a hardware queue. |
| 2123 | * called with controller locked, irqs blocked |
| 2124 | * that hardware queue advances to the next transfer, unless prevented |
| 2125 | */ |
| 2126 | static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) |
| 2127 | { |
| 2128 | struct musb_hw_ep *ep = qh->hw_ep; |
| 2129 | struct musb *musb = ep->musb; |
| 2130 | void __iomem *epio = ep->regs; |
| 2131 | unsigned hw_end = ep->epnum; |
| 2132 | void __iomem *regs = ep->musb->mregs; |
| 2133 | int is_in = usb_pipein(urb->pipe); |
| 2134 | int status = 0; |
| 2135 | u16 csr; |
| 2136 | |
| 2137 | musb_ep_select(regs, hw_end); |
| 2138 | |
| 2139 | if (is_dma_capable()) { |
| 2140 | struct dma_channel *dma; |
| 2141 | |
| 2142 | dma = is_in ? ep->rx_channel : ep->tx_channel; |
| 2143 | if (dma) { |
| 2144 | status = ep->musb->dma_controller->channel_abort(dma); |
| 2145 | dev_dbg(musb->controller, |
| 2146 | "abort %cX%d DMA for urb %p --> %d\n", |
| 2147 | is_in ? 'R' : 'T', ep->epnum, |
| 2148 | urb, status); |
| 2149 | urb->actual_length += dma->actual_len; |
| 2150 | } |
| 2151 | } |
| 2152 | |
| 2153 | /* turn off DMA requests, discard state, stop polling ... */ |
| 2154 | if (ep->epnum && is_in) { |
| 2155 | /* giveback saves bulk toggle */ |
| 2156 | csr = musb_h_flush_rxfifo(ep, 0); |
| 2157 | |
| 2158 | /* REVISIT we still get an irq; should likely clear the |
| 2159 | * endpoint's irq status here to avoid bogus irqs. |
| 2160 | * clearing that status is platform-specific... |
| 2161 | */ |
| 2162 | } else if (ep->epnum) { |
| 2163 | musb_h_tx_flush_fifo(ep); |
| 2164 | csr = musb_readw(epio, MUSB_TXCSR); |
| 2165 | csr &= ~(MUSB_TXCSR_AUTOSET |
| 2166 | | MUSB_TXCSR_DMAENAB |
| 2167 | | MUSB_TXCSR_H_RXSTALL |
| 2168 | | MUSB_TXCSR_H_NAKTIMEOUT |
| 2169 | | MUSB_TXCSR_H_ERROR |
| 2170 | | MUSB_TXCSR_TXPKTRDY); |
| 2171 | musb_writew(epio, MUSB_TXCSR, csr); |
| 2172 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 2173 | musb_writew(epio, MUSB_TXCSR, csr); |
| 2174 | /* flush cpu writebuffer */ |
| 2175 | csr = musb_readw(epio, MUSB_TXCSR); |
| 2176 | } else { |
| 2177 | musb_h_ep0_flush_fifo(ep); |
| 2178 | } |
| 2179 | if (status == 0) |
| 2180 | musb_advance_schedule(ep->musb, urb, ep, is_in); |
| 2181 | return status; |
| 2182 | } |
| 2183 | |
Hans de Goede | 0e4da95 | 2015-01-11 20:34:52 +0100 | [diff] [blame] | 2184 | #ifndef __UBOOT__ |
| 2185 | static int musb_urb_dequeue( |
| 2186 | #else |
| 2187 | int musb_urb_dequeue( |
| 2188 | #endif |
| 2189 | struct usb_hcd *hcd, |
| 2190 | struct urb *urb, |
| 2191 | int status) |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 2192 | { |
| 2193 | struct musb *musb = hcd_to_musb(hcd); |
| 2194 | struct musb_qh *qh; |
| 2195 | unsigned long flags; |
| 2196 | int is_in = usb_pipein(urb->pipe); |
| 2197 | int ret; |
| 2198 | |
| 2199 | dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb, |
| 2200 | usb_pipedevice(urb->pipe), |
| 2201 | usb_pipeendpoint(urb->pipe), |
| 2202 | is_in ? "in" : "out"); |
| 2203 | |
| 2204 | spin_lock_irqsave(&musb->lock, flags); |
| 2205 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); |
| 2206 | if (ret) |
| 2207 | goto done; |
| 2208 | |
| 2209 | qh = urb->hcpriv; |
| 2210 | if (!qh) |
| 2211 | goto done; |
| 2212 | |
| 2213 | /* |
| 2214 | * Any URB not actively programmed into endpoint hardware can be |
| 2215 | * immediately given back; that's any URB not at the head of an |
| 2216 | * endpoint queue, unless someday we get real DMA queues. And even |
| 2217 | * if it's at the head, it might not be known to the hardware... |
| 2218 | * |
| 2219 | * Otherwise abort current transfer, pending DMA, etc.; urb->status |
| 2220 | * has already been updated. This is a synchronous abort; it'd be |
| 2221 | * OK to hold off until after some IRQ, though. |
| 2222 | * |
| 2223 | * NOTE: qh is invalid unless !list_empty(&hep->urb_list) |
| 2224 | */ |
| 2225 | if (!qh->is_ready |
| 2226 | || urb->urb_list.prev != &qh->hep->urb_list |
| 2227 | || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { |
| 2228 | int ready = qh->is_ready; |
| 2229 | |
| 2230 | qh->is_ready = 0; |
| 2231 | musb_giveback(musb, urb, 0); |
| 2232 | qh->is_ready = ready; |
| 2233 | |
| 2234 | /* If nothing else (usually musb_giveback) is using it |
| 2235 | * and its URB list has emptied, recycle this qh. |
| 2236 | */ |
| 2237 | if (ready && list_empty(&qh->hep->urb_list)) { |
| 2238 | qh->hep->hcpriv = NULL; |
| 2239 | list_del(&qh->ring); |
| 2240 | kfree(qh); |
| 2241 | } |
| 2242 | } else |
| 2243 | ret = musb_cleanup_urb(urb, qh); |
| 2244 | done: |
| 2245 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2246 | return ret; |
| 2247 | } |
| 2248 | |
Hans de Goede | 0e4da95 | 2015-01-11 20:34:52 +0100 | [diff] [blame] | 2249 | #ifndef __UBOOT__ |
Ilya Yanok | 06bb920 | 2012-11-06 13:48:21 +0000 | [diff] [blame] | 2250 | /* disable an endpoint */ |
| 2251 | static void |
| 2252 | musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) |
| 2253 | { |
| 2254 | u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; |
| 2255 | unsigned long flags; |
| 2256 | struct musb *musb = hcd_to_musb(hcd); |
| 2257 | struct musb_qh *qh; |
| 2258 | struct urb *urb; |
| 2259 | |
| 2260 | spin_lock_irqsave(&musb->lock, flags); |
| 2261 | |
| 2262 | qh = hep->hcpriv; |
| 2263 | if (qh == NULL) |
| 2264 | goto exit; |
| 2265 | |
| 2266 | /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ |
| 2267 | |
| 2268 | /* Kick the first URB off the hardware, if needed */ |
| 2269 | qh->is_ready = 0; |
| 2270 | if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { |
| 2271 | urb = next_urb(qh); |
| 2272 | |
| 2273 | /* make software (then hardware) stop ASAP */ |
| 2274 | if (!urb->unlinked) |
| 2275 | urb->status = -ESHUTDOWN; |
| 2276 | |
| 2277 | /* cleanup */ |
| 2278 | musb_cleanup_urb(urb, qh); |
| 2279 | |
| 2280 | /* Then nuke all the others ... and advance the |
| 2281 | * queue on hw_ep (e.g. bulk ring) when we're done. |
| 2282 | */ |
| 2283 | while (!list_empty(&hep->urb_list)) { |
| 2284 | urb = next_urb(qh); |
| 2285 | urb->status = -ESHUTDOWN; |
| 2286 | musb_advance_schedule(musb, urb, qh->hw_ep, is_in); |
| 2287 | } |
| 2288 | } else { |
| 2289 | /* Just empty the queue; the hardware is busy with |
| 2290 | * other transfers, and since !qh->is_ready nothing |
| 2291 | * will activate any of these as it advances. |
| 2292 | */ |
| 2293 | while (!list_empty(&hep->urb_list)) |
| 2294 | musb_giveback(musb, next_urb(qh), -ESHUTDOWN); |
| 2295 | |
| 2296 | hep->hcpriv = NULL; |
| 2297 | list_del(&qh->ring); |
| 2298 | kfree(qh); |
| 2299 | } |
| 2300 | exit: |
| 2301 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2302 | } |
| 2303 | |
| 2304 | static int musb_h_get_frame_number(struct usb_hcd *hcd) |
| 2305 | { |
| 2306 | struct musb *musb = hcd_to_musb(hcd); |
| 2307 | |
| 2308 | return musb_readw(musb->mregs, MUSB_FRAME); |
| 2309 | } |
| 2310 | |
| 2311 | static int musb_h_start(struct usb_hcd *hcd) |
| 2312 | { |
| 2313 | struct musb *musb = hcd_to_musb(hcd); |
| 2314 | |
| 2315 | /* NOTE: musb_start() is called when the hub driver turns |
| 2316 | * on port power, or when (OTG) peripheral starts. |
| 2317 | */ |
| 2318 | hcd->state = HC_STATE_RUNNING; |
| 2319 | musb->port1_status = 0; |
| 2320 | return 0; |
| 2321 | } |
| 2322 | |
| 2323 | static void musb_h_stop(struct usb_hcd *hcd) |
| 2324 | { |
| 2325 | musb_stop(hcd_to_musb(hcd)); |
| 2326 | hcd->state = HC_STATE_HALT; |
| 2327 | } |
| 2328 | |
| 2329 | static int musb_bus_suspend(struct usb_hcd *hcd) |
| 2330 | { |
| 2331 | struct musb *musb = hcd_to_musb(hcd); |
| 2332 | u8 devctl; |
| 2333 | |
| 2334 | if (!is_host_active(musb)) |
| 2335 | return 0; |
| 2336 | |
| 2337 | switch (musb->xceiv->state) { |
| 2338 | case OTG_STATE_A_SUSPEND: |
| 2339 | return 0; |
| 2340 | case OTG_STATE_A_WAIT_VRISE: |
| 2341 | /* ID could be grounded even if there's no device |
| 2342 | * on the other end of the cable. NOTE that the |
| 2343 | * A_WAIT_VRISE timers are messy with MUSB... |
| 2344 | */ |
| 2345 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 2346 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) |
| 2347 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
| 2348 | break; |
| 2349 | default: |
| 2350 | break; |
| 2351 | } |
| 2352 | |
| 2353 | if (musb->is_active) { |
| 2354 | WARNING("trying to suspend as %s while active\n", |
| 2355 | otg_state_string(musb->xceiv->state)); |
| 2356 | return -EBUSY; |
| 2357 | } else |
| 2358 | return 0; |
| 2359 | } |
| 2360 | |
| 2361 | static int musb_bus_resume(struct usb_hcd *hcd) |
| 2362 | { |
| 2363 | /* resuming child port does the work */ |
| 2364 | return 0; |
| 2365 | } |
| 2366 | |
| 2367 | const struct hc_driver musb_hc_driver = { |
| 2368 | .description = "musb-hcd", |
| 2369 | .product_desc = "MUSB HDRC host driver", |
| 2370 | .hcd_priv_size = sizeof(struct musb), |
| 2371 | .flags = HCD_USB2 | HCD_MEMORY, |
| 2372 | |
| 2373 | /* not using irq handler or reset hooks from usbcore, since |
| 2374 | * those must be shared with peripheral code for OTG configs |
| 2375 | */ |
| 2376 | |
| 2377 | .start = musb_h_start, |
| 2378 | .stop = musb_h_stop, |
| 2379 | |
| 2380 | .get_frame_number = musb_h_get_frame_number, |
| 2381 | |
| 2382 | .urb_enqueue = musb_urb_enqueue, |
| 2383 | .urb_dequeue = musb_urb_dequeue, |
| 2384 | .endpoint_disable = musb_h_disable, |
| 2385 | |
| 2386 | .hub_status_data = musb_hub_status_data, |
| 2387 | .hub_control = musb_hub_control, |
| 2388 | .bus_suspend = musb_bus_suspend, |
| 2389 | .bus_resume = musb_bus_resume, |
| 2390 | /* .start_port_reset = NULL, */ |
| 2391 | /* .hub_irq_enable = NULL, */ |
| 2392 | }; |
| 2393 | #endif |