| Johnny Huang | d91aaa5 | 2021-10-27 14:17:27 +0800 | [diff] [blame] | 1 | config ASPEED_HACE |
| 2 | bool "ASPEED Hash and Crypto Engine" |
| 3 | depends on DM_HASH |
| 4 | help |
| 5 | Select this option to enable a driver for using the SHA engine in |
| 6 | the ASPEED BMC SoCs. |
| 7 | |
| 8 | Enabling this allows the use of SHA operations in hardware without |
| 9 | requiring the SHA software implementations. It also improves performance |
| 10 | and saves code size. |
| Chia-Wei Wang | 88b3ecf | 2021-10-27 14:17:30 +0800 | [diff] [blame] | 11 | |
| 12 | config ASPEED_ACRY |
| 13 | bool "ASPEED RSA and ECC Engine" |
| 14 | depends on ASPEED_AST2600 |
| 15 | help |
| 16 | Select this option to enable a driver for using the RSA/ECC engine in |
| 17 | the ASPEED BMC SoCs. |
| 18 | |
| 19 | Enabling this allows the use of RSA/ECC operations in hardware without requiring the |
| 20 | software implementations. It also improves performance and saves code size. |
| Chia-Wei Wang | 3827c33 | 2024-08-30 15:23:34 +0800 | [diff] [blame^] | 21 | |
| 22 | config ASPEED_CPTRA_SHA |
| 23 | bool "Caliptra SHA ACC for Aspeed AST27xx SoCs" |
| 24 | depends on DM_HASH |
| 25 | help |
| 26 | Select this option to enable a driver for using the SHA accelerator provided |
| 27 | by Caliptra 1.0, which is integrated in AST27xx BMC SoCs. |
| 28 | |
| 29 | Enabling this allows the use of SHA operations in hardware. Note that only |
| 30 | SHA384 and SHA512 are supported by Caliptra 1.0. |