| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Matrix-centric header file for the AT91SAM9X5 family |
| 3 | * |
| 4 | * Copyright (C) 2012 Atmel Corporation. |
| 5 | * |
| 6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. |
| 7 | * Based on AT91SAM9X5 preliminary datasheet. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __AT91SAM9X5_MATRIX_H__ |
| 16 | #define __AT91SAM9X5_MATRIX_H__ |
| 17 | |
| 18 | #ifndef __ASSEMBLY__ |
| 19 | |
| 20 | struct at91_matrix { |
| 21 | u32 mcfg[16]; |
| 22 | u32 scfg[16]; |
| 23 | u32 pras[16][2]; |
| 24 | u32 mrcr; /* 0x100 Master Remap Control */ |
| 25 | u32 filler[7]; |
| 26 | u32 ebicsa; |
| 27 | u32 filler4[47]; |
| 28 | u32 wpmr; |
| 29 | u32 wpsr; |
| 30 | }; |
| 31 | |
| 32 | #endif /* __ASSEMBLY__ */ |
| 33 | |
| 34 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
| 35 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
| 36 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) |
| 37 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) |
| 38 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
| 39 | #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) |
| 40 | #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) |
| 41 | #define AT91_MATRIX_ULBT_128 (7 << 0) |
| 42 | |
| 43 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
| 44 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
| 45 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
| 46 | #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 |
| 47 | |
| 48 | #define AT91_MATRIX_M0PR_SHIFT 0 |
| 49 | #define AT91_MATRIX_M1PR_SHIFT 4 |
| 50 | #define AT91_MATRIX_M2PR_SHIFT 8 |
| 51 | #define AT91_MATRIX_M3PR_SHIFT 12 |
| 52 | #define AT91_MATRIX_M4PR_SHIFT 16 |
| 53 | #define AT91_MATRIX_M5PR_SHIFT 20 |
| 54 | #define AT91_MATRIX_M6PR_SHIFT 24 |
| 55 | #define AT91_MATRIX_M7PR_SHIFT 28 |
| 56 | |
| 57 | #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ |
| 58 | #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ |
| 59 | #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ |
| 60 | #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ |
| 61 | |
| 62 | #define AT91_MATRIX_RCB0 (1 << 0) |
| 63 | #define AT91_MATRIX_RCB1 (1 << 1) |
| 64 | #define AT91_MATRIX_RCB2 (1 << 2) |
| 65 | #define AT91_MATRIX_RCB3 (1 << 3) |
| 66 | #define AT91_MATRIX_RCB4 (1 << 4) |
| 67 | #define AT91_MATRIX_RCB5 (1 << 5) |
| 68 | #define AT91_MATRIX_RCB6 (1 << 6) |
| 69 | #define AT91_MATRIX_RCB7 (1 << 7) |
| 70 | #define AT91_MATRIX_RCB8 (1 << 8) |
| 71 | #define AT91_MATRIX_RCB9 (1 << 9) |
| 72 | #define AT91_MATRIX_RCB10 (1 << 10) |
| 73 | |
| 74 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) |
| 75 | #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) |
| 76 | #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) |
| 77 | #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) |
| 78 | #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) |
| 79 | #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) |
| 80 | #define AT91_MATRIX_EBI_DBPD_ON (0 << 9) |
| 81 | #define AT91_MATRIX_EBI_DBPD_OFF (1 << 9) |
| 82 | #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) |
| 83 | #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) |
| 84 | #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) |
| 85 | #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) |
| 86 | #define AT91_MATRIX_NFD0_ON_D0 (0 << 24) |
| 87 | #define AT91_MATRIX_NFD0_ON_D16 (1 << 24) |
| 88 | #define AT91_MATRIX_MP_OFF (0 << 25) |
| 89 | #define AT91_MATRIX_MP_ON (1 << 25) |
| 90 | |
| 91 | #endif |