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git01.mediatek.com / filogic / uboot / 37a36b36199b18608789809688faf224b27a8dc6 / . / arch / arm / dts / tegra30-cardhu.dts
blob: ea2cf76ff3a8869c9588a8ff40ceeb489f2d49ee [file] [log] [blame]
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]3#include "tegra30.dtsi"
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]4
5/ {
6 model = "NVIDIA Cardhu";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]9 aliases {
10 i2c0 = "/i2c@7000d000";
11 i2c1 = "/i2c@7000c000";
12 i2c2 = "/i2c@7000c400";
13 i2c3 = "/i2c@7000c500";
14 i2c4 = "/i2c@7000c700";
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]15 sdhci0 = "/sdhci@78000600";
16 sdhci1 = "/sdhci@78000000";
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]17 usb0 = "/usb@7d008000";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]18 };
19
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]20 memory {
21 device_type = "memory";
22 reg = <0x80000000 0x40000000>;
23 };
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]24
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]25 i2c@7000c000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]26 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]27 clock-frequency = <100000>;
28 };
29
30 i2c@7000c400 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]31 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]32 clock-frequency = <100000>;
33 };
34
35 i2c@7000c500 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]36 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]37 clock-frequency = <100000>;
38 };
39
40 i2c@7000c700 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]41 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]42 clock-frequency = <100000>;
43 };
44
45 i2c@7000d000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]46 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]47 clock-frequency = <100000>;
48 };
Allen Martin43b04292013-01-29 13:51:26 +0000[diff] [blame]49
50 spi@7000da00 {
51 status = "okay";
52 spi-max-frequency = <25000000>;
53 };
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]54
55 sdhci@78000000 {
56 status = "okay";
57 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
58 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
59 power-gpios = <&gpio 31 0>; /* gpio PD7 */
60 bus-width = <4>;
61 };
62
63 sdhci@78000600 {
64 status = "okay";
65 bus-width = <8>;
66 };
Jim Lindfed30e2013-06-21 19:05:46 +0800[diff] [blame]67
68 usb@7d008000 {
69 nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
70 status = "okay";
71 };
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]72};