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git01.mediatek.com / filogic / uboot / 3799fbf39a1be79d2b296fec76bbe5536722768a / . / drivers / ddr / imx / phy / ddrphy_utils.c
blob: b852c870f9081280773df27eb7c1b5dd247bbbca [file] [log] [blame]
Ye Lib2cfc422022-07-26 16:41:07 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <errno.h>
8#include <log.h>
9#include <asm/io.h>
10#include <asm/arch/ddr.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/ddr.h>
13#include <asm/arch/sys_proto.h>
14
15static inline void poll_pmu_message_ready(void)
16{
17 unsigned int reg;
18
19 do {
20 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
21 } while (reg & 0x1);
22}
23
24static inline void ack_pmu_message_receive(void)
25{
26 unsigned int reg;
27
28 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0);
29
30 do {
31 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
32 } while (!(reg & 0x1));
33
34 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1);
35}
36
37static inline unsigned int get_mail(void)
38{
39 unsigned int reg;
40
41 poll_pmu_message_ready();
42
43 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
44
45 ack_pmu_message_receive();
46
47 return reg;
48}
49
50static inline unsigned int get_stream_message(void)
51{
52 unsigned int reg, reg2;
53
54 poll_pmu_message_ready();
55
56 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
57
58 reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034));
59
60 reg2 = (reg2 << 16) | reg;
61
62 ack_pmu_message_receive();
63
64 return reg2;
65}
66
67static inline void decode_major_message(unsigned int mail)
68{
69 debug("[PMU Major message = 0x%08x]\n", mail);
70}
71
72static inline void decode_streaming_message(void)
73{
74 unsigned int string_index, arg __maybe_unused;
75 int i = 0;
76
77 string_index = get_stream_message();
78 debug("PMU String index = 0x%08x\n", string_index);
79 while (i < (string_index & 0xffff)) {
80 arg = get_stream_message();
81 debug("arg[%d] = 0x%08x\n", i, arg);
82 i++;
83 }
84
85 debug("\n");
86}
87
88int wait_ddrphy_training_complete(void)
89{
90 unsigned int mail;
91
92 while (1) {
93 mail = get_mail();
94 decode_major_message(mail);
95 if (mail == 0x08) {
96 decode_streaming_message();
97 } else if (mail == 0x07) {
98 debug("Training PASS\n");
99 return 0;
100 } else if (mail == 0xff) {
101 printf("Training FAILED\n");
102 return -1;
103 }
104 }
105}
106
107void ddrphy_init_set_dfi_clk(unsigned int drate)
108{
109 switch (drate) {
110 case 4000:
111 dram_pll_init(MHZ(1000));
112 dram_disable_bypass();
113 break;
114 case 3733:
115 dram_pll_init(MHZ(933));
116 dram_disable_bypass();
117 break;
118 case 3200:
119 dram_pll_init(MHZ(800));
120 dram_disable_bypass();
121 break;
122 case 3000:
123 dram_pll_init(MHZ(750));
124 dram_disable_bypass();
125 break;
126 case 2800:
127 dram_pll_init(MHZ(700));
128 dram_disable_bypass();
129 break;
130 case 2400:
131 dram_pll_init(MHZ(600));
132 dram_disable_bypass();
133 break;
134 case 1866:
135 dram_pll_init(MHZ(466));
136 dram_disable_bypass();
137 break;
138 case 1600:
139 dram_pll_init(MHZ(400));
140 dram_disable_bypass();
141 break;
142 case 1066:
143 dram_pll_init(MHZ(266));
144 dram_disable_bypass();
145 break;
146 case 667:
147 dram_pll_init(MHZ(167));
148 dram_disable_bypass();
149 break;
150 case 400:
151 dram_enable_bypass(MHZ(400));
152 break;
153 case 333:
154 dram_enable_bypass(MHZ(333));
155 break;
156 case 200:
157 dram_enable_bypass(MHZ(200));
158 break;
159 case 100:
160 dram_enable_bypass(MHZ(100));
161 break;
162 default:
163 return;
164 }
165}
166
167void ddrphy_init_read_msg_block(enum fw_type type)
168{
169}