blob: 02a7dc9854753dfad2f277c0ad23a87b5b561eb5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simeke60148d2014-01-14 14:21:52 +01002/*
Michal Simek98d0f1f2018-01-17 07:37:47 +01003 * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
Michal Simeke60148d2014-01-14 14:21:52 +01004 */
5#include <common.h>
Simon Glass091f6a32015-10-17 19:41:22 -06006#include <debug_uart.h>
Simon Glassf11478f2019-12-28 10:45:07 -07007#include <hang.h>
Michal Simeke60148d2014-01-14 14:21:52 +01008#include <spl.h>
Michal Simekdb2337c2020-02-18 15:03:13 +01009#include <generated/dt.h>
Michal Simeke60148d2014-01-14 14:21:52 +010010
11#include <asm/io.h>
Michal Simek162c6372014-08-11 14:03:15 +020012#include <asm/spl.h>
Simon Glass122216d2015-10-17 19:41:21 -060013#include <asm/arch/hardware.h>
Michal Simeke60148d2014-01-14 14:21:52 +010014#include <asm/arch/sys_proto.h>
Michal Simek85dc76a2017-11-08 16:14:47 +010015#include <asm/arch/ps7_init_gpl.h>
Michal Simeke60148d2014-01-14 14:21:52 +010016
Michal Simeke60148d2014-01-14 14:21:52 +010017void board_init_f(ulong dummy)
18{
19 ps7_init();
20
Michal Simeke60148d2014-01-14 14:21:52 +010021 arch_cpu_init();
Michal Simeke533ad22018-04-19 12:36:48 +020022
23#ifdef CONFIG_DEBUG_UART
24 /* Uart debug for sure */
25 debug_uart_init();
26 puts("Debug uart enabled\n"); /* or printch() */
27#endif
Michal Simeke60148d2014-01-14 14:21:52 +010028}
29
Michal Simeka831f1f2014-04-25 12:15:40 +020030#ifdef CONFIG_SPL_BOARD_INIT
31void spl_board_init(void)
32{
Simon Glasse04843d2015-10-19 06:50:02 -060033 preloader_console_init();
Luis Araneda7d9405a2018-07-19 03:10:18 -040034#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
35 arch_early_init_r();
36#endif
Michal Simeka831f1f2014-04-25 12:15:40 +020037 board_init();
38}
39#endif
40
Michal Simeke60148d2014-01-14 14:21:52 +010041u32 spl_boot_device(void)
42{
43 u32 mode;
44
45 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
46#ifdef CONFIG_SPL_SPI_SUPPORT
47 case ZYNQ_BM_QSPI:
Michal Simeke60148d2014-01-14 14:21:52 +010048 mode = BOOT_DEVICE_SPI;
49 break;
50#endif
Michal Simek25830022015-01-13 16:04:10 +010051 case ZYNQ_BM_NAND:
52 mode = BOOT_DEVICE_NAND;
53 break;
54 case ZYNQ_BM_NOR:
55 mode = BOOT_DEVICE_NOR;
56 break;
Michal Simeke60148d2014-01-14 14:21:52 +010057#ifdef CONFIG_SPL_MMC_SUPPORT
58 case ZYNQ_BM_SD:
Michal Simeke60148d2014-01-14 14:21:52 +010059 mode = BOOT_DEVICE_MMC1;
60 break;
61#endif
Michal Simek25830022015-01-13 16:04:10 +010062 case ZYNQ_BM_JTAG:
63 mode = BOOT_DEVICE_RAM;
64 break;
Michal Simeke60148d2014-01-14 14:21:52 +010065 default:
66 puts("Unsupported boot mode selected\n");
67 hang();
68 }
69
70 return mode;
71}
72
Michal Simeke60148d2014-01-14 14:21:52 +010073#ifdef CONFIG_SPL_OS_BOOT
74int spl_start_uboot(void)
75{
76 /* boot linux */
77 return 0;
78}
79#endif
Masahiro Yamadac2d10792014-05-12 12:18:30 +090080
Michal Simek42c8c412016-05-10 07:55:52 +020081void spl_board_prepare_for_boot(void)
82{
83 ps7_post_config();
84 debug("SPL bye\n");
85}
86
Michal Simekf669e222016-05-03 14:20:17 +020087#ifdef CONFIG_SPL_LOAD_FIT
88int board_fit_config_name_match(const char *name)
89{
90 /* Just empty function now - can't decide what to choose */
Michal Simekdb2337c2020-02-18 15:03:13 +010091 debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE);
Michal Simekf669e222016-05-03 14:20:17 +020092
Michal Simekdb2337c2020-02-18 15:03:13 +010093 if (!strcmp(name, DEVICE_TREE))
94 return 0;
95
96 return -1;
Michal Simekf669e222016-05-03 14:20:17 +020097}
98#endif