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Heiko Schocheracb4f4a2006-12-21 16:14:48 +01001/*
Heiko Schocher028c79f2009-09-23 07:56:04 +02002 * (C) Copyright 2003-2009
Heiko Schocheracb4f4a2006-12-21 16:14:48 +01003 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
Heiko Schocher028c79f2009-09-23 07:56:04 +020032#define CONFIG_UC101 1 /* UC101 board */
33#define CONFIG_HOSTNAME uc101
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010034
Heiko Schocher028c79f2009-09-23 07:56:04 +020035#include "manroland/common.h"
36#include "manroland/mpc5200-common.h"
Becky Bruce03ea1be2008-05-08 19:02:12 -050037
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010038/*
39 * Serial console configuration
40 */
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010041#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jon Loeligerc2b1cf02007-07-04 22:33:38 -050042
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010043/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050044 * BOOTP options
45 */
46#define CONFIG_BOOTP_BOOTFILESIZE
47#define CONFIG_BOOTP_BOOTPATH
48#define CONFIG_BOOTP_GATEWAY
49#define CONFIG_BOOTP_HOSTNAME
50
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010051/*
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010052 * Flash configuration
53 */
Heiko Schocher028c79f2009-09-23 07:56:04 +020054#define CONFIG_SYS_MAX_FLASH_SECT 140
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010055
56/*
57 * Environment settings
58 */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020059#define CONFIG_ENV_SECT_SIZE 0x10000
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010060
61/*
62 * Memory map
63 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */
65#define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010066
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010067/* SRAM */
Heiko Schocher028c79f2009-09-23 07:56:04 +020068#define SRAM_BASE CONFIG_SYS_SRAM_BASE
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010069#define SRAM_LEN 0x1fffff
70#define SRAM_END (SRAM_BASE + SRAM_LEN)
71
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010072/*
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010073 * GPIO configuration
74 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010076
Heiko Schocher028c79f2009-09-23 07:56:04 +020077#define CONFIG_SYS_MEMTEST_START 0x00300000
78#define CONFIG_SYS_MEMTEST_END 0x00f00000
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010079
Heiko Schocher028c79f2009-09-23 07:56:04 +020080#define CONFIG_SYS_LOAD_ADDR 0x300000
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010081
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_BOOTCS_CFG 0x00045D00
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010083
84/* 8Mbit SRAM @0x80100000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_CS1_SIZE 0x00200000
86#define CONFIG_SYS_CS1_CFG 0x21D00
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010087
88/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_CS3_START CONFIG_SYS_DISPLAY_BASE
90#define CONFIG_SYS_CS3_SIZE 0x00000100
91#define CONFIG_SYS_CS3_CFG 0x00081802
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010092
93/* Interbus Master 16 Bit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_CS6_START CONFIG_SYS_IB_MASTER
95#define CONFIG_SYS_CS6_SIZE 0x00010000
96#define CONFIG_SYS_CS6_CFG 0x00FF3500
Heiko Schocheracb4f4a2006-12-21 16:14:48 +010097
98/* Interbus EPLD 8 Bit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_CS7_START CONFIG_SYS_IB_EPLD
100#define CONFIG_SYS_CS7_SIZE 0x00010000
101#define CONFIG_SYS_CS7_CFG 0x00081800
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100102
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100103/*-----------------------------------------------------------------------
104 * IDE/ATA stuff Supports IDE harddisk
105 *-----------------------------------------------------------------------
106 */
107
Heiko Schocher028c79f2009-09-23 07:56:04 +0200108#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100109
110/*---------------------------------------------------------------------*/
111/* Display addresses */
112/*---------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
114#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
Heiko Schocheracb4f4a2006-12-21 16:14:48 +0100115
116#endif /* __CONFIG_H */