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Heiko Schocher4e5781b2008-08-21 20:44:49 +02001/*
Heiko Schocher028c79f2009-09-23 07:56:04 +02002 * (C) Copyright 2008-2009
Heiko Schocher4e5781b2008-08-21 20:44:49 +02003 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * (C) Copyright 2003-2005
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
Heiko Schocher028c79f2009-09-23 07:56:04 +020035#define CONFIG_MUCMC52 1 /* MUCMC52 board */
36#define CONFIG_HOSTNAME mucmc52
Heiko Schocher4e5781b2008-08-21 20:44:49 +020037
Heiko Schocher028c79f2009-09-23 07:56:04 +020038#include "manroland/common.h"
39#include "manroland/mpc5200-common.h"
Heiko Schocher4e5781b2008-08-21 20:44:49 +020040
41#define CONFIG_LAST_STAGE_INIT
Heiko Schocher4e5781b2008-08-21 20:44:49 +020042/*
43 * Serial console configuration
44 */
Heiko Schocher4e5781b2008-08-21 20:44:49 +020045#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Heiko Schocher4e5781b2008-08-21 20:44:49 +020046
Heiko Schocher4e5781b2008-08-21 20:44:49 +020047#define CONFIG_CMD_PCI
Heiko Schocher4e5781b2008-08-21 20:44:49 +020048
49/*
Heiko Schocher4e5781b2008-08-21 20:44:49 +020050 * Flash configuration
51 */
Heiko Schocher028c79f2009-09-23 07:56:04 +020052#define CONFIG_SYS_MAX_FLASH_SECT 67
Heiko Schocher4e5781b2008-08-21 20:44:49 +020053
54/*
55 * Environment settings
56 */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020057#define CONFIG_ENV_SECT_SIZE 0x20000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020058
59/*
60 * Memory map
61 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062#define CONFIG_SYS_STATUS1_BASE 0x80600200
63#define CONFIG_SYS_STATUS2_BASE 0x80600300
64#define CONFIG_SYS_PMI_UNI_BASE 0x80800000
65#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020066
Heiko Schocher4e5781b2008-08-21 20:44:49 +020067/*
68 * GPIO configuration
69 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644
Heiko Schocher4e5781b2008-08-21 20:44:49 +020071
Heiko Schocher028c79f2009-09-23 07:56:04 +020072#define CONFIG_SYS_MEMTEST_START 0x00100000
73#define CONFIG_SYS_MEMTEST_END 0x00f00000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020074
Heiko Schocher028c79f2009-09-23 07:56:04 +020075#define CONFIG_SYS_LOAD_ADDR 0x100000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020076
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
Heiko Schocher4e5781b2008-08-21 20:44:49 +020078
79/* 8Mbit SRAM @0x80100000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_CS1_SIZE 0x00100000
81#define CONFIG_SYS_CS1_CFG 0x00019B00
Heiko Schocher4e5781b2008-08-21 20:44:49 +020082
83/* FRAM 32Kbyte @0x80700000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_CS2_START 0x80700000
85#define CONFIG_SYS_CS2_SIZE 0x00008000
86#define CONFIG_SYS_CS2_CFG 0x00019800
Heiko Schocher4e5781b2008-08-21 20:44:49 +020087
88/* Display H1, Status Inputs, EPLD @0x80600000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_CS3_START 0x80600000
90#define CONFIG_SYS_CS3_SIZE 0x00100000
91#define CONFIG_SYS_CS3_CFG 0x00019800
Heiko Schocher4e5781b2008-08-21 20:44:49 +020092
93/* PMI Unicast 32Kbyte @0x80800000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE
95#define CONFIG_SYS_CS6_SIZE 0x00008000
96#define CONFIG_SYS_CS6_CFG 0xFFFFF930
Heiko Schocher4e5781b2008-08-21 20:44:49 +020097
98/* PMI Broadcast 32Kbyte @0x80810000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE
100#define CONFIG_SYS_CS7_SIZE 0x00008000
101#define CONFIG_SYS_CS7_CFG 0xFF00F930
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200102
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200103/*-----------------------------------------------------------------------
104 * IDE/ATA stuff Supports IDE harddisk
105 *-----------------------------------------------------------------------
106 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200108
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200109/*
110 * PCI Mapping:
111 * 0x40000000 - 0x4fffffff - PCI Memory
112 * 0x50000000 - 0x50ffffff - PCI IO Space
113 */
114#define CONFIG_PCI 1
115#define CONFIG_PCI_PNP 1
116#define CONFIG_PCI_SCAN_SHOW 1
117#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
118
119#define CONFIG_PCI_MEM_BUS 0x40000000
120#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
121#define CONFIG_PCI_MEM_SIZE 0x10000000
122
123#define CONFIG_PCI_IO_BUS 0x50000000
124#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
125#define CONFIG_PCI_IO_SIZE 0x01000000
126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200128
129/*---------------------------------------------------------------------*/
130/* Display addresses */
131/*---------------------------------------------------------------------*/
132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
134#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200135
136#endif /* __CONFIG_H */