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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk024a26b2002-08-21 21:35:08 +00002/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk024a26b2002-08-21 21:35:08 +00005 */
6
Wolfgang Denka1be4762008-05-20 16:00:29 +02007#include <linux/types.h> /* for ulong typedef */
wdenk024a26b2002-08-21 21:35:08 +00008
9#ifndef _FPGA_H_
10#define _FPGA_H_
11
12#ifndef CONFIG_MAX_FPGA_DEVICES
13#define CONFIG_MAX_FPGA_DEVICES 5
14#endif
15
wdenk024a26b2002-08-21 21:35:08 +000016/* fpga_xxxx function return value definitions */
Wolfgang Denka1be4762008-05-20 16:00:29 +020017#define FPGA_SUCCESS 0
Alexander Dahla839c562019-06-28 14:41:24 +020018#define FPGA_FAIL 1
wdenk024a26b2002-08-21 21:35:08 +000019
20/* device numbers must be non-negative */
Wolfgang Denka1be4762008-05-20 16:00:29 +020021#define FPGA_INVALID_DEVICE -1
wdenk024a26b2002-08-21 21:35:08 +000022
Adrian Fiergolski0d6bb432022-07-22 17:16:14 +030023#define FPGA_ENC_DEV_KEY 0
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053024#define FPGA_ENC_USR_KEY 1
25#define FPGA_NO_ENC_OR_NO_AUTH 2
26
wdenk024a26b2002-08-21 21:35:08 +000027/* root data type defintions */
Wolfgang Denka1be4762008-05-20 16:00:29 +020028typedef enum { /* typedef fpga_type */
29 fpga_min_type, /* range check value */
30 fpga_xilinx, /* Xilinx Family) */
31 fpga_altera, /* unimplemented */
Stefano Babicec65c592010-06-29 11:47:48 +020032 fpga_lattice, /* Lattice family */
Wolfgang Denka1be4762008-05-20 16:00:29 +020033 fpga_undefined /* invalid range check value */
34} fpga_type; /* end, typedef fpga_type */
wdenk024a26b2002-08-21 21:35:08 +000035
Wolfgang Denka1be4762008-05-20 16:00:29 +020036typedef struct { /* typedef fpga_desc */
37 fpga_type devtype; /* switch value to select sub-functions */
38 void *devdesc; /* real device descriptor */
39} fpga_desc; /* end, typedef fpga_desc */
wdenk024a26b2002-08-21 21:35:08 +000040
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053041typedef struct { /* typedef fpga_desc */
42 unsigned int blocksize;
43 char *interface;
44 char *dev_part;
Tien Fong Chee3b45f6b2019-02-15 15:57:07 +080045 const char *filename;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053046 int fstype;
47} fpga_fs_info;
wdenk024a26b2002-08-21 21:35:08 +000048
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053049struct fpga_secure_info {
50 u8 *userkey_addr;
51 u8 authflag;
52 u8 encflag;
53};
54
Michal Simek14663652014-05-02 14:09:30 +020055typedef enum {
56 BIT_FULL = 0,
Michal Simek64c70982014-05-02 13:43:39 +020057 BIT_PARTIAL,
Siva Durga Prasad Paladugu589aa772015-12-09 18:46:42 +053058 BIT_NONE = 0xFF,
Michal Simek14663652014-05-02 14:09:30 +020059} bitstream_type;
60
wdenk024a26b2002-08-21 21:35:08 +000061/* root function definitions */
Michal Simek6e297ac2015-01-14 09:59:00 +010062void fpga_init(void);
63int fpga_add(fpga_type devtype, void *desc);
64int fpga_count(void);
Michal Simekfbadb762015-01-13 16:09:53 +010065const fpga_desc *const fpga_get_desc(int devnum);
Goldschmidt Simon9179c812017-11-10 14:17:41 +000066int fpga_is_partial_data(int devnum, size_t img_len);
Michal Simek6e297ac2015-01-14 09:59:00 +010067int fpga_load(int devnum, const void *buf, size_t bsize,
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +030068 bitstream_type bstype, int flags);
Michal Simek6e297ac2015-01-14 09:59:00 +010069int fpga_fsload(int devnum, const void *buf, size_t size,
70 fpga_fs_info *fpga_fsinfo);
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053071int fpga_loads(int devnum, const void *buf, size_t size,
72 struct fpga_secure_info *fpga_sec_info);
Michal Simek6e297ac2015-01-14 09:59:00 +010073int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
74 bitstream_type bstype);
75int fpga_dump(int devnum, const void *buf, size_t bsize);
76int fpga_info(int devnum);
77const fpga_desc *const fpga_validate(int devnum, const void *buf,
78 size_t bsize, char *fn);
Oleksandr Suvorova4d95932022-07-22 17:16:08 +030079int fpga_compatible2flag(int devnum, const char *compatible);
wdenk024a26b2002-08-21 21:35:08 +000080
81#endif /* _FPGA_H_ */