Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 7 | #include <linux/types.h> /* for ulong typedef */ |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 8 | |
| 9 | #ifndef _FPGA_H_ |
| 10 | #define _FPGA_H_ |
| 11 | |
| 12 | #ifndef CONFIG_MAX_FPGA_DEVICES |
| 13 | #define CONFIG_MAX_FPGA_DEVICES 5 |
| 14 | #endif |
| 15 | |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 16 | /* fpga_xxxx function return value definitions */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 17 | #define FPGA_SUCCESS 0 |
Alexander Dahl | a839c56 | 2019-06-28 14:41:24 +0200 | [diff] [blame] | 18 | #define FPGA_FAIL 1 |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 19 | |
| 20 | /* device numbers must be non-negative */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 21 | #define FPGA_INVALID_DEVICE -1 |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 22 | |
Adrian Fiergolski | 0d6bb43 | 2022-07-22 17:16:14 +0300 | [diff] [blame] | 23 | #define FPGA_ENC_DEV_KEY 0 |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 24 | #define FPGA_ENC_USR_KEY 1 |
| 25 | #define FPGA_NO_ENC_OR_NO_AUTH 2 |
| 26 | |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 27 | /* root data type defintions */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 28 | typedef enum { /* typedef fpga_type */ |
| 29 | fpga_min_type, /* range check value */ |
| 30 | fpga_xilinx, /* Xilinx Family) */ |
| 31 | fpga_altera, /* unimplemented */ |
Stefano Babic | ec65c59 | 2010-06-29 11:47:48 +0200 | [diff] [blame] | 32 | fpga_lattice, /* Lattice family */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 33 | fpga_undefined /* invalid range check value */ |
| 34 | } fpga_type; /* end, typedef fpga_type */ |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 35 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 36 | typedef struct { /* typedef fpga_desc */ |
| 37 | fpga_type devtype; /* switch value to select sub-functions */ |
| 38 | void *devdesc; /* real device descriptor */ |
| 39 | } fpga_desc; /* end, typedef fpga_desc */ |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 40 | |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 41 | typedef struct { /* typedef fpga_desc */ |
| 42 | unsigned int blocksize; |
| 43 | char *interface; |
| 44 | char *dev_part; |
Tien Fong Chee | 3b45f6b | 2019-02-15 15:57:07 +0800 | [diff] [blame] | 45 | const char *filename; |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 46 | int fstype; |
| 47 | } fpga_fs_info; |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 48 | |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 49 | struct fpga_secure_info { |
| 50 | u8 *userkey_addr; |
| 51 | u8 authflag; |
| 52 | u8 encflag; |
| 53 | }; |
| 54 | |
Michal Simek | 1466365 | 2014-05-02 14:09:30 +0200 | [diff] [blame] | 55 | typedef enum { |
| 56 | BIT_FULL = 0, |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 57 | BIT_PARTIAL, |
Siva Durga Prasad Paladugu | 589aa77 | 2015-12-09 18:46:42 +0530 | [diff] [blame] | 58 | BIT_NONE = 0xFF, |
Michal Simek | 1466365 | 2014-05-02 14:09:30 +0200 | [diff] [blame] | 59 | } bitstream_type; |
| 60 | |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 61 | /* root function definitions */ |
Michal Simek | 6e297ac | 2015-01-14 09:59:00 +0100 | [diff] [blame] | 62 | void fpga_init(void); |
| 63 | int fpga_add(fpga_type devtype, void *desc); |
| 64 | int fpga_count(void); |
Michal Simek | fbadb76 | 2015-01-13 16:09:53 +0100 | [diff] [blame] | 65 | const fpga_desc *const fpga_get_desc(int devnum); |
Goldschmidt Simon | 9179c81 | 2017-11-10 14:17:41 +0000 | [diff] [blame] | 66 | int fpga_is_partial_data(int devnum, size_t img_len); |
Michal Simek | 6e297ac | 2015-01-14 09:59:00 +0100 | [diff] [blame] | 67 | int fpga_load(int devnum, const void *buf, size_t bsize, |
Oleksandr Suvorov | 4ff163d | 2022-07-22 17:16:07 +0300 | [diff] [blame] | 68 | bitstream_type bstype, int flags); |
Michal Simek | 6e297ac | 2015-01-14 09:59:00 +0100 | [diff] [blame] | 69 | int fpga_fsload(int devnum, const void *buf, size_t size, |
| 70 | fpga_fs_info *fpga_fsinfo); |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 71 | int fpga_loads(int devnum, const void *buf, size_t size, |
| 72 | struct fpga_secure_info *fpga_sec_info); |
Michal Simek | 6e297ac | 2015-01-14 09:59:00 +0100 | [diff] [blame] | 73 | int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, |
| 74 | bitstream_type bstype); |
| 75 | int fpga_dump(int devnum, const void *buf, size_t bsize); |
| 76 | int fpga_info(int devnum); |
| 77 | const fpga_desc *const fpga_validate(int devnum, const void *buf, |
| 78 | size_t bsize, char *fn); |
Oleksandr Suvorov | a4d9593 | 2022-07-22 17:16:08 +0300 | [diff] [blame] | 79 | int fpga_compatible2flag(int devnum, const char *compatible); |
wdenk | 024a26b | 2002-08-21 21:35:08 +0000 | [diff] [blame] | 80 | |
| 81 | #endif /* _FPGA_H_ */ |