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Simon Glass8c0629b2019-12-08 17:40:08 -07001// SPDX-License-Identifier: GPL-2.0
2/*
Wolfgang Wallner12ea8582020-01-22 16:01:44 +01003 * Interrupt Timer Subsystem
Simon Glass8c0629b2019-12-08 17:40:08 -07004 *
5 * Copyright (C) 2017 Intel Corporation.
6 * Copyright (C) 2017 Siemens AG
7 * Copyright 2019 Google LLC
8 *
9 * Taken from coreboot itss.c
10 */
11
12#include <common.h>
13#include <dm.h>
14#include <dt-structs.h>
15#include <irq.h>
16#include <p2sb.h>
17#include <spl.h>
Wolfgang Wallner97132162020-01-22 16:01:45 +010018#include <asm/itss.h>
Simon Glass8c0629b2019-12-08 17:40:08 -070019
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010020struct itss_platdata {
Simon Glass8c0629b2019-12-08 17:40:08 -070021#if CONFIG_IS_ENABLED(OF_PLATDATA)
22 /* Put this first since driver model will copy the data here */
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010023 struct dtd_intel_itss dtplat;
Simon Glass8c0629b2019-12-08 17:40:08 -070024#endif
25};
26
27/* struct pmc_route - Routing for PMC to GPIO */
28struct pmc_route {
29 u32 pmc;
30 u32 gpio;
31};
32
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010033struct itss_priv {
Simon Glass8c0629b2019-12-08 17:40:08 -070034 struct pmc_route *route;
35 uint route_count;
36 u32 irq_snapshot[NUM_IPC_REGS];
37};
38
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010039static int set_polarity(struct udevice *dev, uint irq, bool active_low)
Simon Glass8c0629b2019-12-08 17:40:08 -070040{
41 u32 mask;
42 uint reg;
43
44 if (irq > ITSS_MAX_IRQ)
45 return -EINVAL;
46
47 reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * (irq / IRQS_PER_IPC);
48 mask = 1 << (irq % IRQS_PER_IPC);
49
50 pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0);
51
52 return 0;
53}
54
55#ifndef CONFIG_TPL_BUILD
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010056static int snapshot_polarities(struct udevice *dev)
Simon Glass8c0629b2019-12-08 17:40:08 -070057{
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010058 struct itss_priv *priv = dev_get_priv(dev);
Simon Glass8c0629b2019-12-08 17:40:08 -070059 const int start = GPIO_IRQ_START;
60 const int end = GPIO_IRQ_END;
61 int reg_start;
62 int reg_end;
63 int i;
64
65 reg_start = start / IRQS_PER_IPC;
66 reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
67
68 for (i = reg_start; i < reg_end; i++) {
69 uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
70
71 priv->irq_snapshot[i] = pcr_read32(dev, reg);
72 }
73
74 return 0;
75}
76
77static void show_polarities(struct udevice *dev, const char *msg)
78{
79 int i;
80
81 log_info("ITSS IRQ Polarities %s:\n", msg);
82 for (i = 0; i < NUM_IPC_REGS; i++) {
83 uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
84
85 log_info("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
86 }
87}
88
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010089static int restore_polarities(struct udevice *dev)
Simon Glass8c0629b2019-12-08 17:40:08 -070090{
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +010091 struct itss_priv *priv = dev_get_priv(dev);
Simon Glass8c0629b2019-12-08 17:40:08 -070092 const int start = GPIO_IRQ_START;
93 const int end = GPIO_IRQ_END;
94 int reg_start;
95 int reg_end;
96 int i;
97
98 show_polarities(dev, "Before");
99
100 reg_start = start / IRQS_PER_IPC;
101 reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
102
103 for (i = reg_start; i < reg_end; i++) {
104 u32 mask;
105 u16 reg;
106 int irq_start;
107 int irq_end;
108
109 irq_start = i * IRQS_PER_IPC;
110 irq_end = min(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ);
111
112 if (start > irq_end)
113 continue;
114 if (end < irq_start)
115 break;
116
117 /* Track bits within the bounds of of the register */
118 irq_start = max(start, irq_start) % IRQS_PER_IPC;
119 irq_end = min(end, irq_end) % IRQS_PER_IPC;
120
121 /* Create bitmask of the inclusive range of start and end */
122 mask = (((1U << irq_end) - 1) | (1U << irq_end));
123 mask &= ~((1U << irq_start) - 1);
124
125 reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
126 pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
127 }
128
129 show_polarities(dev, "After");
130
131 return 0;
132}
133#endif
134
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100135static int route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
Simon Glass8c0629b2019-12-08 17:40:08 -0700136{
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100137 struct itss_priv *priv = dev_get_priv(dev);
Simon Glass8c0629b2019-12-08 17:40:08 -0700138 struct pmc_route *route;
139 int i;
140
141 for (i = 0, route = priv->route; i < priv->route_count; i++, route++) {
142 if (pmc_gpe_num == route->pmc)
143 return route->gpio;
144 }
145
146 return -ENOENT;
147}
148
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100149static int itss_ofdata_to_platdata(struct udevice *dev)
Simon Glass8c0629b2019-12-08 17:40:08 -0700150{
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100151 struct itss_priv *priv = dev_get_priv(dev);
Simon Glass8c0629b2019-12-08 17:40:08 -0700152 int ret;
153
154#if CONFIG_IS_ENABLED(OF_PLATDATA)
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100155 struct itss_platdata *plat = dev_get_platdata(dev);
156 struct dtd_intel_itss *dtplat = &plat->dtplat;
Simon Glass8c0629b2019-12-08 17:40:08 -0700157
158 /*
159 * It would be nice to do this in the bind() method, but with
160 * of-platdata binding happens in the order that DM finds things in the
161 * linker list (i.e. alphabetical order by driver name). So the GPIO
162 * device may well be bound before its parent (p2sb), and this call
163 * will fail if p2sb is not bound yet.
164 *
165 * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
166 */
167 ret = p2sb_set_port_id(dev, dtplat->intel_p2sb_port_id);
168 if (ret)
169 return log_msg_ret("Could not set port id", ret);
170 priv->route = (struct pmc_route *)dtplat->intel_pmc_routes;
171 priv->route_count = ARRAY_SIZE(dtplat->intel_pmc_routes) /
172 sizeof(struct pmc_route);
173#else
174 int size;
175
176 size = dev_read_size(dev, "intel,pmc-routes");
177 if (size < 0)
178 return size;
179 priv->route = malloc(size);
180 if (!priv->route)
181 return -ENOMEM;
182 ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route,
183 size / sizeof(fdt32_t));
184 if (ret)
185 return log_msg_ret("Cannot read pmc-routes", ret);
186 priv->route_count = size / sizeof(struct pmc_route);
187#endif
188
189 return 0;
190}
191
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100192static const struct irq_ops itss_ops = {
193 .route_pmc_gpio_gpe = route_pmc_gpio_gpe,
194 .set_polarity = set_polarity,
Simon Glass8c0629b2019-12-08 17:40:08 -0700195#ifndef CONFIG_TPL_BUILD
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100196 .snapshot_polarities = snapshot_polarities,
197 .restore_polarities = restore_polarities,
Simon Glass8c0629b2019-12-08 17:40:08 -0700198#endif
199};
200
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100201static const struct udevice_id itss_ids[] = {
202 { .compatible = "intel,itss"},
Simon Glass8c0629b2019-12-08 17:40:08 -0700203 { }
204};
205
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100206U_BOOT_DRIVER(itss_drv) = {
207 .name = "intel_itss",
Simon Glass8c0629b2019-12-08 17:40:08 -0700208 .id = UCLASS_IRQ,
Wolfgang Wallner3767e7f2020-01-22 16:01:47 +0100209 .of_match = itss_ids,
210 .ops = &itss_ops,
211 .ofdata_to_platdata = itss_ofdata_to_platdata,
212 .platdata_auto_alloc_size = sizeof(struct itss_platdata),
213 .priv_auto_alloc_size = sizeof(struct itss_priv),
Simon Glass8c0629b2019-12-08 17:40:08 -0700214};