Tom Warren | 1ded602 | 2011-01-27 10:58:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010,2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <ns16550.h> |
| 26 | #include <asm/io.h> |
| 27 | #include <asm/arch/tegra2.h> |
| 28 | #include "serial_tegra2.h" |
| 29 | |
| 30 | static void setup_uart(struct uart_ctlr *u) |
| 31 | { |
| 32 | u32 reg; |
| 33 | |
| 34 | /* Prepare the divisor value */ |
| 35 | reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16; |
| 36 | |
| 37 | /* Set up UART parameters */ |
| 38 | writel(UART_LCR_DLAB, &u->uart_lcr); |
| 39 | writel(reg, &u->uart_thr_dlab_0); |
| 40 | writel(0, &u->uart_ier_dlab_0); |
| 41 | writel(0, &u->uart_lcr); /* clear DLAB */ |
| 42 | writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \ |
| 43 | UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr); |
| 44 | writel(0, &u->uart_ier_dlab_0); |
| 45 | writel(UART_LCR_WLS_8, &u->uart_lcr); /* 8N1 */ |
| 46 | writel(UART_MCR_RTS, &u->uart_mcr); |
| 47 | writel(0, &u->uart_msr); |
| 48 | writel(0, &u->uart_spr); |
| 49 | writel(0, &u->uart_irda_csr); |
| 50 | writel(0, &u->uart_asr); |
| 51 | writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr); |
| 52 | |
| 53 | /* Flush any old characters out of the RX FIFO */ |
| 54 | reg = readl(&u->uart_lsr); |
| 55 | |
| 56 | while (reg & UART_LSR_DR) { |
| 57 | reg = readl(&u->uart_thr_dlab_0); |
| 58 | reg = readl(&u->uart_lsr); |
| 59 | } |
| 60 | } |
| 61 | |
| 62 | /* |
| 63 | * Routine: uart_init |
| 64 | * Description: init the UART clocks, muxes, and baudrate/parity/etc. |
| 65 | */ |
| 66 | void uart_init(void) |
| 67 | { |
| 68 | struct uart_ctlr *uart = (struct uart_ctlr *)NV_PA_APB_UARTD_BASE; |
| 69 | #if defined(CONFIG_TEGRA2_ENABLE_UARTD) |
| 70 | setup_uart(uart); |
| 71 | #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ |
| 72 | #if defined(CONFIG_TEGRA2_ENABLE_UARTA) |
| 73 | uart = (struct uart_ctlr *)NV_PA_APB_UARTA_BASE; |
| 74 | |
| 75 | setup_uart(uart); |
| 76 | #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ |
| 77 | } |