Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2016 Freescale Semiconductor |
Pankit Garg | b45d6ce | 2019-05-30 12:04:14 +0000 | [diff] [blame] | 4 | * Copyright 2019 NXP |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __LS1046ARDB_H__ |
| 8 | #define __LS1046ARDB_H__ |
| 9 | |
| 10 | #include "ls1046a_common.h" |
| 11 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 12 | /* Physical Memory Map */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 13 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 14 | #define SPD_EEPROM_ADDRESS 0x51 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 15 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 16 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 17 | |
Tom Rini | 9ff815a | 2021-08-24 23:11:49 -0400 | [diff] [blame] | 18 | #if defined(CONFIG_QSPI_BOOT) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 19 | #define CFG_SYS_UBOOT_BASE 0x40100000 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 20 | #endif |
| 21 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 22 | #define CFG_SYS_NAND_BASE 0x7e800000 |
| 23 | #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 24 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 25 | #define CFG_SYS_NAND_CSPR_EXT (0x0) |
| 26 | #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 27 | | CSPR_PORT_SIZE_8 \ |
| 28 | | CSPR_MSEL_NAND \ |
| 29 | | CSPR_V) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 30 | #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) |
| 31 | #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 32 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 33 | | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ |
| 34 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
| 35 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ |
| 36 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ |
| 37 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
| 38 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 39 | #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 40 | FTIM0_NAND_TWP(0x18) | \ |
| 41 | FTIM0_NAND_TWCHT(0x7) | \ |
| 42 | FTIM0_NAND_TWH(0xa)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 43 | #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 44 | FTIM1_NAND_TWBE(0x39) | \ |
| 45 | FTIM1_NAND_TRR(0xe) | \ |
| 46 | FTIM1_NAND_TRP(0x18)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 47 | #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 48 | FTIM2_NAND_TREH(0xa) | \ |
| 49 | FTIM2_NAND_TWHRE(0x1e)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 50 | #define CFG_SYS_NAND_FTIM3 0x0 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 51 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 52 | #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 53 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 54 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 55 | /* |
| 56 | * CPLD |
| 57 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 58 | #define CFG_SYS_CPLD_BASE 0x7fb00000 |
| 59 | #define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 60 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 61 | #define CFG_SYS_CPLD_CSPR_EXT (0x0) |
| 62 | #define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 63 | CSPR_PORT_SIZE_8 | \ |
| 64 | CSPR_MSEL_GPCM | \ |
| 65 | CSPR_V) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 66 | #define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) |
| 67 | #define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 68 | |
| 69 | /* CPLD Timing parameters for IFC GPCM */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 70 | #define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 71 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 72 | FTIM0_GPCM_TEAHC(0x0e)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 73 | #define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 74 | FTIM1_GPCM_TRAD(0x3f)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 75 | #define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 76 | FTIM2_GPCM_TCH(0xf) | \ |
| 77 | FTIM2_GPCM_TWP(0x3E)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 78 | #define CFG_SYS_CPLD_FTIM3 0x0 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 79 | |
| 80 | /* IFC Timing Params */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 81 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT |
| 82 | #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR |
| 83 | #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK |
| 84 | #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR |
| 85 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 |
| 86 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 |
| 87 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 |
| 88 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 89 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 90 | #define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT |
| 91 | #define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR |
| 92 | #define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK |
| 93 | #define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR |
| 94 | #define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 |
| 95 | #define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 |
| 96 | #define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 |
| 97 | #define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 98 | |
| 99 | /* EEPROM */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 100 | #define I2C_RETIMER_ADDR 0x18 |
| 101 | |
Hou Zhiqiang | 67b6d0a | 2016-12-09 16:09:01 +0800 | [diff] [blame] | 102 | /* PMIC */ |
Hou Zhiqiang | 67b6d0a | 2016-12-09 16:09:01 +0800 | [diff] [blame] | 103 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 104 | /* |
| 105 | * Environment |
| 106 | */ |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 107 | #define CFG_SYS_FSL_QSPI_BASE 0x40000000 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 108 | |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 109 | #define AQR105_IRQ_MASK 0x80000000 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 110 | /* FMan */ |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 111 | #ifndef SPL_NO_FMAN |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 112 | #ifdef CONFIG_SYS_DPAA_FMAN |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 113 | #define RGMII_PHY1_ADDR 0x1 |
| 114 | #define RGMII_PHY2_ADDR 0x2 |
| 115 | |
| 116 | #define SGMII_PHY1_ADDR 0x3 |
| 117 | #define SGMII_PHY2_ADDR 0x4 |
| 118 | |
| 119 | #define FM1_10GEC1_PHY_ADDR 0x0 |
| 120 | |
Prabhakar Kushwaha | a512261 | 2017-11-23 16:51:48 +0530 | [diff] [blame] | 121 | #define FDT_SEQ_MACADDR_FROM_ENV |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 122 | #endif |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 123 | |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 124 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 125 | |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 126 | #ifndef SPL_NO_MISC |
Rajesh Bhagat | cb6153b | 2018-11-05 18:02:36 +0000 | [diff] [blame] | 127 | #ifdef CONFIG_TFABOOT |
| 128 | #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ |
| 129 | "env exists secureboot && esbc_halt;;" |
| 130 | #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ |
| 131 | "env exists secureboot && esbc_halt;" |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 132 | #endif |
Rajesh Bhagat | cb6153b | 2018-11-05 18:02:36 +0000 | [diff] [blame] | 133 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 134 | |
Vinitha Pillai-B57223 | a47072e | 2017-03-23 13:48:18 +0530 | [diff] [blame] | 135 | #include <asm/fsl_secure_boot.h> |
| 136 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 137 | #endif /* __LS1046ARDB_H__ */ |