blob: 211dab4d23372f1628458f80ebed30b89fcdb772 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrena3e280b2011-01-27 10:58:07 +00002/*
Stephen Warrenc7382852012-05-21 10:04:27 +00003 * (C) Copyright 2010-2012
Tom Warrena3e280b2011-01-27 10:58:07 +00004 * NVIDIA Corporation <www.nvidia.com>
Tom Warrena3e280b2011-01-27 10:58:07 +00005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Alexey Brodkin267d8e22014-02-26 17:47:58 +040010#include <linux/sizes.h>
Allen Martin55d98a12012-08-31 08:30:00 +000011#include "tegra20-common.h"
Tom Warrena3e280b2011-01-27 10:58:07 +000012
13/* High-level configuration options */
Tom Warren22562a42012-09-04 17:00:24 -070014#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
Tom Warrena3e280b2011-01-27 10:58:07 +000015
16/* Board-specific serial config */
Tom Warren22562a42012-09-04 17:00:24 -070017#define CONFIG_TEGRA_ENABLE_UARTD
Tom Warrena3e280b2011-01-27 10:58:07 +000018
19/* UARTD: keyboard satellite board UART, default */
Tom Rinidf6a2152022-11-16 13:10:28 -050020#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
Tom Warren22562a42012-09-04 17:00:24 -070021#ifdef CONFIG_TEGRA_ENABLE_UARTA
Tom Warrena3e280b2011-01-27 10:58:07 +000022/* UARTA: debug board UART */
Tom Rinidf6a2152022-11-16 13:10:28 -050023#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
Tom Warrena3e280b2011-01-27 10:58:07 +000024#endif
25
Stephen Warren560a1ee2012-07-30 07:37:52 +000026/* NAND support */
Stephen Warren560a1ee2012-07-30 07:37:52 +000027
28/* Environment in NAND (which is 512M), aligned to start of last sector */
Stephen Warrende17c292012-05-16 06:21:00 +000029
Tom Warren22562a42012-09-04 17:00:24 -070030#include "tegra-common-post.h"
Stephen Warrende17c292012-05-16 06:21:00 +000031
Tom Warrena3e280b2011-01-27 10:58:07 +000032#endif /* __CONFIG_H */