blob: dd322c2b3a79787b9da5c3e42dfd2e8fced199b8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +05302/*
3 * Copyright (C) 2013 Samsung Electronics
4 *
5 * Configuration settings for the SAMSUNG EXYNOS5 board.
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +05306 */
7
Simon Glassbe165002014-10-07 22:01:44 -06008#ifndef __CONFIG_EXYNOS5_COMMON_H
9#define __CONFIG_EXYNOS5_COMMON_H
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053010
Simon Glass14e27ab2014-10-07 22:01:45 -060011#include "exynos-common.h"
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053012
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053013/* Power Down Modes */
14#define S5P_CHECK_SLEEP 0x00000BAD
15#define S5P_CHECK_DIDLE 0xBAD00000
16#define S5P_CHECK_LPA 0xABAD0000
17
18/* Offset for inform registers */
19#define INFORM0_OFFSET 0x800
20#define INFORM1_OFFSET 0x804
21#define INFORM2_OFFSET 0x808
22#define INFORM3_OFFSET 0x80c
23
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053024/* select serial console configuration */
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053025#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053026
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053027/* MMC SPL */
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053028#define COPY_BL2_FNPTR_ADDR 0x02020030
29
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053030#define CONFIG_RD_LVL
31
Tom Rinibb4dd962022-11-16 13:10:37 -050032#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053033#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050034#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053035#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050036#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053037#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050038#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053039#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050040#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053041#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050042#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053043#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050044#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053045#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050046#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053047#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
48
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053049/* SPI */
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053050
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053051/* Ethernet Controllor Driver */
52#ifdef CONFIG_CMD_NET
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053053#define CONFIG_ENV_SROM_BANK 1
54#endif /*CONFIG_CMD_NET*/
55
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053056/* Enable Time Command */
Rajeshwari Birje194fa0a2013-12-26 09:44:26 +053057
Sjoerd Simons1a5d7212014-12-29 22:17:10 +010058/* USB */
Sjoerd Simons1a5d7212014-12-29 22:17:10 +010059
Akshay Saraswat5cae4122014-06-18 17:54:01 +053060/* USB boot mode */
61#define CONFIG_USB_BOOTING
62#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
63#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
64#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
65
Ian Campbell3ecaa402014-11-09 10:44:32 +000066#define BOOT_TARGET_DEVICES(func) \
Guillaume GARDET3d9bbb02019-07-24 09:10:13 +020067 func(MMC, mmc, 2) \
Ian Campbell3ecaa402014-11-09 10:44:32 +000068 func(MMC, mmc, 1) \
69 func(MMC, mmc, 0) \
70 func(PXE, pxe, na) \
71 func(DHCP, dhcp, na)
72
73#include <config_distro_bootcmd.h>
74
75#ifndef MEM_LAYOUT_ENV_SETTINGS
76/* 2GB RAM, bootm size of 256M, load scripts after that */
77#define MEM_LAYOUT_ENV_SETTINGS \
78 "bootm_size=0x10000000\0" \
79 "kernel_addr_r=0x42000000\0" \
80 "fdt_addr_r=0x43000000\0" \
81 "ramdisk_addr_r=0x43300000\0" \
82 "scriptaddr=0x50000000\0" \
83 "pxefile_addr_r=0x51000000\0"
84#endif
85
86#ifndef EXYNOS_DEVICE_SETTINGS
87#define EXYNOS_DEVICE_SETTINGS \
88 "stdin=serial\0" \
89 "stdout=serial\0" \
90 "stderr=serial\0"
91#endif
92
93#ifndef EXYNOS_FDTFILE_SETTING
94#define EXYNOS_FDTFILE_SETTING
95#endif
96
97#define CONFIG_EXTRA_ENV_SETTINGS \
98 EXYNOS_DEVICE_SETTINGS \
99 EXYNOS_FDTFILE_SETTING \
100 MEM_LAYOUT_ENV_SETTINGS \
101 BOOTENV
102
Simon Glassbe165002014-10-07 22:01:44 -0600103#endif /* __CONFIG_EXYNOS5_COMMON_H */