Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 Samsung Electronics |
| 4 | * |
| 5 | * Configuration settings for the SAMSUNG EXYNOS5 board. |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Simon Glass | be16500 | 2014-10-07 22:01:44 -0600 | [diff] [blame] | 8 | #ifndef __CONFIG_EXYNOS5_COMMON_H |
| 9 | #define __CONFIG_EXYNOS5_COMMON_H |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 10 | |
Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 11 | #include "exynos-common.h" |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 12 | |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 13 | /* Power Down Modes */ |
| 14 | #define S5P_CHECK_SLEEP 0x00000BAD |
| 15 | #define S5P_CHECK_DIDLE 0xBAD00000 |
| 16 | #define S5P_CHECK_LPA 0xABAD0000 |
| 17 | |
| 18 | /* Offset for inform registers */ |
| 19 | #define INFORM0_OFFSET 0x800 |
| 20 | #define INFORM1_OFFSET 0x804 |
| 21 | #define INFORM2_OFFSET 0x808 |
| 22 | #define INFORM3_OFFSET 0x80c |
| 23 | |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 24 | /* select serial console configuration */ |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 25 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 26 | |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 27 | /* MMC SPL */ |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 28 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
| 29 | |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 30 | #define CONFIG_RD_LVL |
| 31 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 32 | #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 33 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 34 | #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 35 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 36 | #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 37 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 38 | #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 39 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 40 | #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 41 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 42 | #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 43 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 44 | #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 45 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 46 | #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 47 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE |
| 48 | |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 49 | /* SPI */ |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 50 | |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 51 | /* Ethernet Controllor Driver */ |
| 52 | #ifdef CONFIG_CMD_NET |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 53 | #define CONFIG_ENV_SROM_BANK 1 |
| 54 | #endif /*CONFIG_CMD_NET*/ |
| 55 | |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 56 | /* Enable Time Command */ |
Rajeshwari Birje | 194fa0a | 2013-12-26 09:44:26 +0530 | [diff] [blame] | 57 | |
Sjoerd Simons | 1a5d721 | 2014-12-29 22:17:10 +0100 | [diff] [blame] | 58 | /* USB */ |
Sjoerd Simons | 1a5d721 | 2014-12-29 22:17:10 +0100 | [diff] [blame] | 59 | |
Akshay Saraswat | 5cae412 | 2014-06-18 17:54:01 +0530 | [diff] [blame] | 60 | /* USB boot mode */ |
| 61 | #define CONFIG_USB_BOOTING |
| 62 | #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 |
| 63 | #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 |
| 64 | #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 |
| 65 | |
Ian Campbell | 3ecaa40 | 2014-11-09 10:44:32 +0000 | [diff] [blame] | 66 | #define BOOT_TARGET_DEVICES(func) \ |
Guillaume GARDET | 3d9bbb0 | 2019-07-24 09:10:13 +0200 | [diff] [blame] | 67 | func(MMC, mmc, 2) \ |
Ian Campbell | 3ecaa40 | 2014-11-09 10:44:32 +0000 | [diff] [blame] | 68 | func(MMC, mmc, 1) \ |
| 69 | func(MMC, mmc, 0) \ |
| 70 | func(PXE, pxe, na) \ |
| 71 | func(DHCP, dhcp, na) |
| 72 | |
| 73 | #include <config_distro_bootcmd.h> |
| 74 | |
| 75 | #ifndef MEM_LAYOUT_ENV_SETTINGS |
| 76 | /* 2GB RAM, bootm size of 256M, load scripts after that */ |
| 77 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 78 | "bootm_size=0x10000000\0" \ |
| 79 | "kernel_addr_r=0x42000000\0" \ |
| 80 | "fdt_addr_r=0x43000000\0" \ |
| 81 | "ramdisk_addr_r=0x43300000\0" \ |
| 82 | "scriptaddr=0x50000000\0" \ |
| 83 | "pxefile_addr_r=0x51000000\0" |
| 84 | #endif |
| 85 | |
| 86 | #ifndef EXYNOS_DEVICE_SETTINGS |
| 87 | #define EXYNOS_DEVICE_SETTINGS \ |
| 88 | "stdin=serial\0" \ |
| 89 | "stdout=serial\0" \ |
| 90 | "stderr=serial\0" |
| 91 | #endif |
| 92 | |
| 93 | #ifndef EXYNOS_FDTFILE_SETTING |
| 94 | #define EXYNOS_FDTFILE_SETTING |
| 95 | #endif |
| 96 | |
| 97 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 98 | EXYNOS_DEVICE_SETTINGS \ |
| 99 | EXYNOS_FDTFILE_SETTING \ |
| 100 | MEM_LAYOUT_ENV_SETTINGS \ |
| 101 | BOOTENV |
| 102 | |
Simon Glass | be16500 | 2014-10-07 22:01:44 -0600 | [diff] [blame] | 103 | #endif /* __CONFIG_EXYNOS5_COMMON_H */ |