Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
Yangbo Lu | bb32e68 | 2021-06-03 10:51:19 +0800 | [diff] [blame] | 4 | * Copyright 2020-2021 NXP |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
Shengzhou Liu | 031228a | 2014-02-21 13:16:19 +0800 | [diff] [blame] | 8 | * T2080/T2081 QDS board configuration file |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 9 | */ |
| 10 | |
Shengzhou Liu | 031228a | 2014-02-21 13:16:19 +0800 | [diff] [blame] | 11 | #ifndef __T208xQDS_H |
| 12 | #define __T208xQDS_H |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 13 | |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 14 | #include <linux/stringify.h> |
| 15 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 16 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 17 | |
| 18 | /* High Level Configuration Options */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 19 | |
Tom Rini | 0a2bac7 | 2022-11-16 13:10:29 -0500 | [diff] [blame] | 20 | #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 21 | |
| 22 | #ifdef CONFIG_RAMBOOT_PBL |
Shengzhou Liu | d11b3cb | 2014-04-18 16:43:39 +0800 | [diff] [blame] | 23 | #define RESET_VECTOR_OFFSET 0x27FFC |
| 24 | #define BOOT_PAGE_OFFSET 0x27000 |
Shengzhou Liu | d11b3cb | 2014-04-18 16:43:39 +0800 | [diff] [blame] | 25 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 26 | #ifdef CONFIG_MTD_RAW_NAND |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 27 | #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| 28 | #define CFG_SYS_NAND_U_BOOT_DST 0x00200000 |
| 29 | #define CFG_SYS_NAND_U_BOOT_START 0x00200000 |
Shengzhou Liu | d11b3cb | 2014-04-18 16:43:39 +0800 | [diff] [blame] | 30 | #endif |
| 31 | |
| 32 | #ifdef CONFIG_SPIFLASH |
| 33 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 34 | #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
| 35 | #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) |
| 36 | #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) |
| 37 | #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
Shengzhou Liu | d11b3cb | 2014-04-18 16:43:39 +0800 | [diff] [blame] | 38 | #endif |
| 39 | |
| 40 | #ifdef CONFIG_SDCARD |
| 41 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 42 | #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 43 | #define CFG_SYS_MMC_U_BOOT_DST (0x00200000) |
| 44 | #define CFG_SYS_MMC_U_BOOT_START (0x00200000) |
| 45 | #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 46 | #endif |
| 47 | |
Shengzhou Liu | d11b3cb | 2014-04-18 16:43:39 +0800 | [diff] [blame] | 48 | #endif /* CONFIG_RAMBOOT_PBL */ |
| 49 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 50 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
| 51 | /* Set 1M boot space */ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 52 | #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) |
| 53 | #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ |
| 54 | (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 55 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 56 | #endif |
| 57 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 58 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 59 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 60 | #endif |
| 61 | |
| 62 | /* |
| 63 | * These can be toggled for performance analysis, otherwise use default. |
| 64 | */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 65 | #ifdef CONFIG_DDR_ECC |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 66 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 67 | #endif |
| 68 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 69 | /* |
| 70 | * Config the L3 Cache as L3 SRAM |
| 71 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 72 | #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 |
Tom Rini | 5cd7ece | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 73 | #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 74 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 75 | #define CFG_SYS_DCSRBAR 0xf0000000 |
| 76 | #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 77 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 78 | /* |
| 79 | * DDR Setup |
| 80 | */ |
| 81 | #define CONFIG_VERY_BIG_RAM |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 82 | #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 83 | #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 84 | #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 85 | #define SPD_EEPROM_ADDRESS1 0x51 |
| 86 | #define SPD_EEPROM_ADDRESS2 0x52 |
| 87 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 |
| 88 | #define CTRL_INTLV_PREFERED cacheline |
| 89 | |
| 90 | /* |
| 91 | * IFC Definitions |
| 92 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 93 | #define CFG_SYS_FLASH_BASE 0xe0000000 |
| 94 | #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) |
| 95 | #define CFG_SYS_NOR0_CSPR_EXT (0xf) |
| 96 | #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 97 | + 0x8000000) | \ |
| 98 | CSPR_PORT_SIZE_16 | \ |
| 99 | CSPR_MSEL_NOR | \ |
| 100 | CSPR_V) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 101 | #define CFG_SYS_NOR1_CSPR_EXT (0xf) |
| 102 | #define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 103 | CSPR_PORT_SIZE_16 | \ |
| 104 | CSPR_MSEL_NOR | \ |
| 105 | CSPR_V) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 106 | #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 107 | /* NOR Flash Timing Params */ |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 108 | #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 109 | |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 110 | #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 111 | FTIM0_NOR_TEADC(0x5) | \ |
| 112 | FTIM0_NOR_TEAHC(0x5)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 113 | #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 114 | FTIM1_NOR_TRAD_NOR(0x1A) |\ |
| 115 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 116 | #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 117 | FTIM2_NOR_TCH(0x4) | \ |
| 118 | FTIM2_NOR_TWPH(0x0E) | \ |
| 119 | FTIM2_NOR_TWP(0x1c)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 120 | #define CFG_SYS_NOR_FTIM3 0x0 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 121 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 122 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 123 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 124 | #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ |
| 125 | + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 126 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 127 | #define QIXIS_BASE 0xffdf0000 |
| 128 | #define QIXIS_LBMAP_SWITCH 6 |
| 129 | #define QIXIS_LBMAP_MASK 0x0f |
| 130 | #define QIXIS_LBMAP_SHIFT 0 |
| 131 | #define QIXIS_LBMAP_DFLTBANK 0x00 |
| 132 | #define QIXIS_LBMAP_ALTBANK 0x04 |
York Sun | 23b3df9 | 2016-04-07 09:52:11 -0700 | [diff] [blame] | 133 | #define QIXIS_LBMAP_NAND 0x09 |
| 134 | #define QIXIS_LBMAP_SD 0x00 |
| 135 | #define QIXIS_RCW_SRC_NAND 0x104 |
| 136 | #define QIXIS_RCW_SRC_SD 0x040 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 137 | #define QIXIS_RST_CTL_RESET 0x83 |
| 138 | #define QIXIS_RST_FORCE_MEM 0x1 |
| 139 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 140 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
| 141 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
| 142 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) |
| 143 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 144 | #define CFG_SYS_CSPR3_EXT (0xf) |
| 145 | #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 146 | | CSPR_PORT_SIZE_8 \ |
| 147 | | CSPR_MSEL_GPCM \ |
| 148 | | CSPR_V) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 149 | #define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) |
| 150 | #define CFG_SYS_CSOR3 0x0 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 151 | /* QIXIS Timing parameters for IFC CS3 */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 152 | #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 153 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 154 | FTIM0_GPCM_TEAHC(0x0e)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 155 | #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 156 | FTIM1_GPCM_TRAD(0x3f)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 157 | #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
Shengzhou Liu | bdfeaf6 | 2014-03-06 15:07:39 +0800 | [diff] [blame] | 158 | FTIM2_GPCM_TCH(0x8) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 159 | FTIM2_GPCM_TWP(0x1f)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 160 | #define CFG_SYS_CS3_FTIM3 0x0 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 161 | |
| 162 | /* NAND Flash on IFC */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 163 | #define CFG_SYS_NAND_BASE 0xff800000 |
| 164 | #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 165 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 166 | #define CFG_SYS_NAND_CSPR_EXT (0xf) |
| 167 | #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 168 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ |
| 169 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ |
| 170 | | CSPR_V) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 171 | #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 172 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 173 | #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 174 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 175 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 176 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ |
| 177 | | CSOR_NAND_PGS_2K /* Page Size = 2K */\ |
| 178 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ |
| 179 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
| 180 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 181 | /* ONFI NAND Flash mode0 Timing Params */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 182 | #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 183 | FTIM0_NAND_TWP(0x18) | \ |
| 184 | FTIM0_NAND_TWCHT(0x07) | \ |
| 185 | FTIM0_NAND_TWH(0x0a)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 186 | #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 187 | FTIM1_NAND_TWBE(0x39) | \ |
| 188 | FTIM1_NAND_TRR(0x0e) | \ |
| 189 | FTIM1_NAND_TRP(0x18)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 190 | #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 191 | FTIM2_NAND_TREH(0x0a) | \ |
| 192 | FTIM2_NAND_TWHRE(0x1e)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 193 | #define CFG_SYS_NAND_FTIM3 0x0 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 194 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 195 | #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 196 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 197 | #if defined(CONFIG_MTD_RAW_NAND) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 198 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT |
| 199 | #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR |
| 200 | #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK |
| 201 | #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR |
| 202 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 |
| 203 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 |
| 204 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 |
| 205 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 |
| 206 | #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT |
| 207 | #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR |
| 208 | #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK |
| 209 | #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR |
| 210 | #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 |
| 211 | #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 |
| 212 | #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 |
| 213 | #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 |
| 214 | #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT |
| 215 | #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR |
| 216 | #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK |
| 217 | #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR |
| 218 | #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 |
| 219 | #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 |
| 220 | #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 |
| 221 | #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 222 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 223 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT |
| 224 | #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR |
| 225 | #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK |
| 226 | #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR |
| 227 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 |
| 228 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 |
| 229 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 |
| 230 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 |
| 231 | #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT |
| 232 | #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR |
| 233 | #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK |
| 234 | #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR |
| 235 | #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 |
| 236 | #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 |
| 237 | #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 |
| 238 | #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 |
| 239 | #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT |
| 240 | #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR |
| 241 | #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK |
| 242 | #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR |
| 243 | #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 |
| 244 | #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 |
| 245 | #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 |
| 246 | #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 247 | #endif |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 248 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 249 | /* define to use L1 as initial stack */ |
| 250 | #define CONFIG_L1_INIT_RAM |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 251 | #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
| 252 | #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
| 253 | #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 254 | /* The assembler doesn't like typecast */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 255 | #define CFG_SYS_INIT_RAM_ADDR_PHYS \ |
| 256 | ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 257 | CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
| 258 | #define CFG_SYS_INIT_RAM_SIZE 0x00004000 |
| 259 | #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 260 | |
| 261 | /* |
| 262 | * Serial Port |
| 263 | */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 264 | #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 265 | #define CFG_SYS_BAUDRATE_TABLE \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 266 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 267 | #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) |
| 268 | #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) |
| 269 | #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) |
| 270 | #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 271 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 272 | /* |
| 273 | * I2C |
| 274 | */ |
Biwen Li | 07b3dcf | 2020-05-01 20:04:19 +0800 | [diff] [blame] | 275 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 276 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
| 277 | #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ |
| 278 | #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ |
| 279 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 280 | |
Ying Zhang | 8876a51 | 2014-10-31 18:06:18 +0800 | [diff] [blame] | 281 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
| 282 | |
| 283 | /* Voltage monitor on channel 2*/ |
| 284 | #define I2C_VOL_MONITOR_ADDR 0x40 |
| 285 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 |
| 286 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 |
| 287 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 |
| 288 | |
Ying Zhang | 8876a51 | 2014-10-31 18:06:18 +0800 | [diff] [blame] | 289 | /* The lowest and highest voltage allowed for T208xQDS */ |
| 290 | #define VDD_MV_MIN 819 |
| 291 | #define VDD_MV_MAX 1212 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 292 | |
| 293 | /* |
| 294 | * RapidIO |
| 295 | */ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 296 | #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
| 297 | #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
| 298 | #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
| 299 | #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 |
| 300 | #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
| 301 | #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 302 | /* |
| 303 | * for slave u-boot IMAGE instored in master memory space, |
| 304 | * PHYS must be aligned based on the SIZE |
| 305 | */ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 306 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 307 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull |
| 308 | #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ |
| 309 | #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 310 | /* |
| 311 | * for slave UCODE and ENV instored in master memory space, |
| 312 | * PHYS must be aligned based on the SIZE |
| 313 | */ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 314 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| 315 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
| 316 | #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 317 | |
| 318 | /* slave core release by master*/ |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 319 | #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
| 320 | #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 321 | |
| 322 | /* |
| 323 | * SRIO_PCIE_BOOT - SLAVE |
| 324 | */ |
| 325 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
Tom Rini | 40eb556 | 2022-11-16 13:10:40 -0500 | [diff] [blame] | 326 | #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 |
| 327 | #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ |
| 328 | (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 329 | #endif |
| 330 | |
| 331 | /* |
| 332 | * eSPI - Enhanced SPI |
| 333 | */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 334 | |
| 335 | /* |
| 336 | * General PCI |
| 337 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 338 | */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 339 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 340 | #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 341 | #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 342 | #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| 343 | #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 344 | |
| 345 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 346 | #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 347 | #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 348 | #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| 349 | #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 350 | |
| 351 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 352 | #define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 |
| 353 | #define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 354 | |
| 355 | /* controller 4, Base address 203000 */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 356 | #define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 |
| 357 | #define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 358 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 359 | /* Qman/Bman */ |
| 360 | #ifndef CONFIG_NOBQFMAN |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 361 | #define CFG_SYS_BMAN_NUM_PORTALS 18 |
| 362 | #define CFG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 363 | #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
| 364 | #define CFG_SYS_BMAN_MEM_SIZE 0x02000000 |
| 365 | #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 366 | #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 |
| 367 | #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE |
| 368 | #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) |
| 369 | #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ |
| 370 | CFG_SYS_BMAN_CENA_SIZE) |
| 371 | #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) |
| 372 | #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
| 373 | #define CFG_SYS_QMAN_NUM_PORTALS 18 |
| 374 | #define CFG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 375 | #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
| 376 | #define CFG_SYS_QMAN_MEM_SIZE 0x02000000 |
| 377 | #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 |
| 378 | #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) |
| 379 | #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ |
| 380 | CFG_SYS_QMAN_CENA_SIZE) |
| 381 | #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) |
| 382 | #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 383 | #endif /* CONFIG_NOBQFMAN */ |
| 384 | |
| 385 | #ifdef CONFIG_SYS_DPAA_FMAN |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 386 | #define RGMII_PHY1_ADDR 0x1 |
| 387 | #define RGMII_PHY2_ADDR 0x2 |
| 388 | #define FM1_10GEC1_PHY_ADDR 0x3 |
| 389 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C |
| 390 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D |
| 391 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E |
| 392 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F |
| 393 | #endif |
| 394 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 395 | /* |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 396 | * USB |
| 397 | */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 398 | |
| 399 | /* |
| 400 | * SDHC |
| 401 | */ |
| 402 | #ifdef CONFIG_MMC |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 403 | #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 404 | #endif |
| 405 | |
Shengzhou Liu | ff16bd8 | 2014-04-02 14:28:34 +0800 | [diff] [blame] | 406 | /* |
| 407 | * Dynamic MTD Partition support with mtdparts |
| 408 | */ |
Shengzhou Liu | ff16bd8 | 2014-04-02 14:28:34 +0800 | [diff] [blame] | 409 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 410 | /* |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 411 | * Miscellaneous configurable options |
| 412 | */ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 413 | |
| 414 | /* |
| 415 | * For booting Linux, the board info and command line data |
| 416 | * have to be in the first 64 MB of memory, since this is |
| 417 | * the maximum mapped by the Linux kernel during initialization. |
| 418 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 419 | #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 420 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 421 | /* |
| 422 | * Environment Configuration |
| 423 | */ |
| 424 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 425 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ |
| 426 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 427 | #define __USB_PHY_TYPE utmi |
| 428 | |
| 429 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 430 | "hwconfig=fsl_ddr:" \ |
| 431 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ |
| 432 | "bank_intlv=auto;" \ |
| 433 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ |
| 434 | "netdev=eth0\0" \ |
| 435 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 436 | "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 437 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 438 | "protect off $ubootaddr +$filesize && " \ |
| 439 | "erase $ubootaddr +$filesize && " \ |
| 440 | "cp.b $loadaddr $ubootaddr $filesize && " \ |
| 441 | "protect on $ubootaddr +$filesize && " \ |
| 442 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| 443 | "consoledev=ttyS0\0" \ |
| 444 | "ramdiskaddr=2000000\0" \ |
| 445 | "ramdiskfile=t2080qds/ramdisk.uboot\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 446 | "fdtaddr=1e00000\0" \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 447 | "fdtfile=t2080qds/t2080qds.dtb\0" \ |
Kim Phillips | 1dedccc | 2014-05-14 19:33:45 -0500 | [diff] [blame] | 448 | "bdev=sda3\0" |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 449 | |
| 450 | /* |
| 451 | * For emulation this causes u-boot to jump to the start of the |
| 452 | * proof point app code automatically |
| 453 | */ |
Tom Rini | 9aed2af | 2021-08-19 14:29:00 -0400 | [diff] [blame] | 454 | #define PROOF_POINTS \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 455 | "setenv bootargs root=/dev/$bdev rw " \ |
| 456 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 457 | "cpu 1 release 0x29000000 - - -;" \ |
| 458 | "cpu 2 release 0x29000000 - - -;" \ |
| 459 | "cpu 3 release 0x29000000 - - -;" \ |
| 460 | "cpu 4 release 0x29000000 - - -;" \ |
| 461 | "cpu 5 release 0x29000000 - - -;" \ |
| 462 | "cpu 6 release 0x29000000 - - -;" \ |
| 463 | "cpu 7 release 0x29000000 - - -;" \ |
| 464 | "go 0x29000000" |
| 465 | |
Tom Rini | 9aed2af | 2021-08-19 14:29:00 -0400 | [diff] [blame] | 466 | #define HVBOOT \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 467 | "setenv bootargs config-addr=0x60000000; " \ |
| 468 | "bootm 0x01000000 - 0x00f00000" |
| 469 | |
Tom Rini | 9aed2af | 2021-08-19 14:29:00 -0400 | [diff] [blame] | 470 | #define ALU \ |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 471 | "setenv bootargs root=/dev/$bdev rw " \ |
| 472 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 473 | "cpu 1 release 0x01000000 - - -;" \ |
| 474 | "cpu 2 release 0x01000000 - - -;" \ |
| 475 | "cpu 3 release 0x01000000 - - -;" \ |
| 476 | "cpu 4 release 0x01000000 - - -;" \ |
| 477 | "cpu 5 release 0x01000000 - - -;" \ |
| 478 | "cpu 6 release 0x01000000 - - -;" \ |
| 479 | "cpu 7 release 0x01000000 - - -;" \ |
| 480 | "go 0x01000000" |
| 481 | |
Shengzhou Liu | 0788694 | 2013-11-22 17:39:11 +0800 | [diff] [blame] | 482 | #include <asm/fsl_secure_boot.h> |
Aneesh Bansal | 962021a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 483 | |
Shengzhou Liu | 031228a | 2014-02-21 13:16:19 +0800 | [diff] [blame] | 484 | #endif /* __T208xQDS_H */ |