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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewb859ef12007-08-16 19:23:50 -05002/*
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewb859ef12007-08-16 19:23:50 -05007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M5235EVB_H
14#define _M5235EVB_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChungLiewb859ef12007-08-16 19:23:50 -050020
Tom Rini6a5dccc2022-11-16 13:10:41 -050021#define CFG_SYS_UART_PORT (0)
TsiChungLiewb859ef12007-08-16 19:23:50 -050022
TsiChungLiewb859ef12007-08-16 19:23:50 -050023#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
24
TsiChungLiewb859ef12007-08-16 19:23:50 -050025/* I2C */
Tom Rini6a5dccc2022-11-16 13:10:41 -050026#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
27#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
28#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
TsiChungLiewb859ef12007-08-16 19:23:50 -050029
Patrick Delaunayfd501c02021-10-04 11:59:50 +020030/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
TsiChungLiewb859ef12007-08-16 19:23:50 -050031#ifdef CONFIG_MCFFEC
TsiChungLiewb859ef12007-08-16 19:23:50 -050032# define CONFIG_IPADDR 192.162.1.2
33# define CONFIG_NETMASK 255.255.255.0
34# define CONFIG_SERVERIP 192.162.1.1
35# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewb859ef12007-08-16 19:23:50 -050036#endif /* FEC_ENET */
37
Mario Six790d8442018-03-28 14:38:20 +020038#define CONFIG_HOSTNAME "M5235EVB"
TsiChungLiewb859ef12007-08-16 19:23:50 -050039#define CONFIG_EXTRA_ENV_SETTINGS \
40 "netdev=eth0\0" \
41 "loadaddr=10000\0" \
42 "u-boot=u-boot.bin\0" \
43 "load=tftp ${loadaddr) ${u-boot}\0" \
44 "upd=run load; run prog\0" \
45 "prog=prot off ffe00000 ffe3ffff;" \
46 "era ffe00000 ffe3ffff;" \
47 "cp.b ${loadaddr} ffe00000 ${filesize};"\
48 "save\0" \
49 ""
50
51#define CONFIG_PRAM 512 /* 512 KB */
TsiChungLiewb859ef12007-08-16 19:23:50 -050052
Tom Rini6a5dccc2022-11-16 13:10:41 -050053#define CFG_SYS_CLK 75000000
54#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2
TsiChungLiewb859ef12007-08-16 19:23:50 -050055
Tom Rini6a5dccc2022-11-16 13:10:41 -050056#define CFG_SYS_MBAR 0x40000000
TsiChungLiewb859ef12007-08-16 19:23:50 -050057
58/*
59 * Low Level Configuration Settings
60 * (address mappings, register initial values, etc.)
61 * You should know what you are doing if you make changes here.
62 */
63/*-----------------------------------------------------------------------
64 * Definitions for initial stack pointer and data area (in DPRAM)
65 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050066#define CFG_SYS_INIT_RAM_ADDR 0x20000000
67#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
68#define CFG_SYS_INIT_RAM_CTRL 0x21
TsiChungLiewb859ef12007-08-16 19:23:50 -050069
70/*-----------------------------------------------------------------------
71 * Start addresses for the final memory configuration
72 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -050073 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewb859ef12007-08-16 19:23:50 -050074 */
Tom Rinibb4dd962022-11-16 13:10:37 -050075#define CFG_SYS_SDRAM_BASE 0x00000000
76#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChungLiewb859ef12007-08-16 19:23:50 -050077
TsiChungLiewb859ef12007-08-16 19:23:50 -050078/*
79 * For booting Linux, the board info and command line data
80 * have to be in the first 8 MB of memory, since this is
81 * the maximum mapped by the Linux kernel during initialization ??
82 */
83/* Initial Memory map for Linux */
Tom Rini6a5dccc2022-11-16 13:10:41 -050084#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
TsiChungLiewb859ef12007-08-16 19:23:50 -050085
86/*-----------------------------------------------------------------------
87 * FLASH organization
88 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#ifdef CONFIG_SYS_FLASH_CFI
Tom Rini6a5dccc2022-11-16 13:10:41 -050090# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
TsiChungLiewb859ef12007-08-16 19:23:50 -050091#endif
92
Tom Rini6a5dccc2022-11-16 13:10:41 -050093#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
TsiChungLiewb859ef12007-08-16 19:23:50 -050094
95/* Configuration for environment
96 * Environment is embedded in u-boot in the second sector of the flash
97 */
angelo@sysam.it6312a952015-03-29 22:54:16 +020098
99#define LDS_BOARD_TEXT \
100 . = DEFINED(env_offset) ? env_offset : .; \
Simon Glass547cb402017-08-03 12:21:49 -0600101 env/embedded.o(.text);
angelo@sysam.it6312a952015-03-29 22:54:16 +0200102
TsiChungLiewb859ef12007-08-16 19:23:50 -0500103/*-----------------------------------------------------------------------
104 * Cache Configuration
105 */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500106
Tom Rini6a5dccc2022-11-16 13:10:41 -0500107#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
108 CFG_SYS_INIT_RAM_SIZE - 8)
109#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
110 CFG_SYS_INIT_RAM_SIZE - 4)
111#define CFG_SYS_ICACHE_INV (CF_CACR_CINV)
112#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -0500113 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600114 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500115#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600116 CF_CACR_CEIB | CF_CACR_DCM | \
117 CF_CACR_EUSP)
118
TsiChungLiewb859ef12007-08-16 19:23:50 -0500119/*-----------------------------------------------------------------------
120 * Chipselect bank definitions
121 */
122/*
123 * CS0 - NOR Flash 1, 2, 4, or 8MB
124 * CS1 - Available
125 * CS2 - Available
126 * CS3 - Available
127 * CS4 - Available
128 * CS5 - Available
129 * CS6 - Available
130 * CS7 - Available
131 */
Tom Rini9823f5e2022-03-24 17:18:04 -0400132#ifdef CONFIG_NORFLASH_PS32BIT
Tom Rini6a5dccc2022-11-16 13:10:41 -0500133# define CFG_SYS_CS0_BASE 0xFFC00000
134# define CFG_SYS_CS0_MASK 0x003f0001
135# define CFG_SYS_CS0_CTRL 0x00001D00
TsiChungLiewb859ef12007-08-16 19:23:50 -0500136#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500137# define CFG_SYS_CS0_BASE 0xFFE00000
138# define CFG_SYS_CS0_MASK 0x001f0001
139# define CFG_SYS_CS0_CTRL 0x00001D80
TsiChungLiewb859ef12007-08-16 19:23:50 -0500140#endif
141
142#endif /* _M5329EVB_H */