| Michal Simek | b091b88 | 2016-03-18 23:45:02 +0100 | [diff] [blame] | 1 | XILINX_ZYNQMP BOARDS |
| Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 2 | M: Michal Simek <michal.simek@xilinx.com> |
| 3 | S: Maintained |
| Michal Simek | 0cdefc2 | 2018-03-13 11:07:25 +0100 | [diff] [blame] | 4 | F: arch/arm/dts/zynqmp-* |
| Michal Simek | 07a7e0a | 2019-06-20 08:02:46 +0200 | [diff] [blame] | 5 | F: arch/arm/dts/avnet-ultra96* |
| Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 6 | F: board/xilinx/zynqmp/ |
| Michal Simek | b091b88 | 2016-03-18 23:45:02 +0100 | [diff] [blame] | 7 | F: include/configs/xilinx_zynqmp* |
| 8 | F: configs/xilinx_zynqmp* |
| Tom Rini | 28c8664 | 2018-08-07 11:36:39 -0400 | [diff] [blame] | 9 | F: configs/avnet_ultra96_rev1_defconfig |
| Luca Ceresoli | 5b5d1cf | 2019-06-20 18:18:16 +0200 | [diff] [blame] | 10 | |
| 11 | ARM ZYNQMP AVNET ULTRAZED EV BOARD |
| 12 | M: Luca Ceresoli <luca@lucaceresoli.net> |
| 13 | S: Maintained |
| 14 | F: arch/arm/dts/avnet-ultrazedev-* |
| 15 | F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig |