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git01.mediatek.com / filogic / uboot / 36f83d9e9e2cf40f95716004b8bbafd211faa762 / . / arch / arm / dts / r8a7796.dtsi
blob: c0cb4a952f289ccabec91bb7d28f57222e3c97a7 [file] [log] [blame]
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]1/*
2 * Device Tree Source for the r8a7796 SoC
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/power/r8a7796-sysc.h>
14
15/ {
16 compatible = "renesas,r8a7796";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
28 i2c7 = &i2c_dvfs;
29 };
30
31 psci {
32 compatible = "arm,psci-1.0", "arm,psci-0.2";
33 method = "smc";
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 a57_0: cpu@0 {
41 compatible = "arm,cortex-a57", "arm,armv8";
42 reg = <0x0>;
43 device_type = "cpu";
44 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
45 next-level-cache = <&L2_CA57>;
46 enable-method = "psci";
47 };
48
49 a57_1: cpu@1 {
50 compatible = "arm,cortex-a57","arm,armv8";
51 reg = <0x1>;
52 device_type = "cpu";
53 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
54 next-level-cache = <&L2_CA57>;
55 enable-method = "psci";
56 };
57
58 a53_0: cpu@100 {
59 compatible = "arm,cortex-a53", "arm,armv8";
60 reg = <0x100>;
61 device_type = "cpu";
62 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
63 next-level-cache = <&L2_CA53>;
64 enable-method = "psci";
65 };
66
67 a53_1: cpu@101 {
68 compatible = "arm,cortex-a53","arm,armv8";
69 reg = <0x101>;
70 device_type = "cpu";
71 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
72 next-level-cache = <&L2_CA53>;
73 enable-method = "psci";
74 };
75
76 a53_2: cpu@102 {
77 compatible = "arm,cortex-a53","arm,armv8";
78 reg = <0x102>;
79 device_type = "cpu";
80 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
81 next-level-cache = <&L2_CA53>;
82 enable-method = "psci";
83 };
84
85 a53_3: cpu@103 {
86 compatible = "arm,cortex-a53","arm,armv8";
87 reg = <0x103>;
88 device_type = "cpu";
89 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
90 next-level-cache = <&L2_CA53>;
91 enable-method = "psci";
92 };
93
94 L2_CA57: cache-controller-0 {
95 compatible = "cache";
96 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
97 cache-unified;
98 cache-level = <2>;
99 };
100
101 L2_CA53: cache-controller-1 {
102 compatible = "cache";
103 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
104 cache-unified;
105 cache-level = <2>;
106 };
107 };
108
109 extal_clk: extal {
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 /* This value must be overridden by the board */
113 clock-frequency = <0>;
Marek Vasut7c084002017-08-20 17:13:40 +0200[diff] [blame]114 u-boot,dm-pre-reloc;
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]115 };
116
117 extalr_clk: extalr {
118 compatible = "fixed-clock";
119 #clock-cells = <0>;
120 /* This value must be overridden by the board */
121 clock-frequency = <0>;
Marek Vasut7c084002017-08-20 17:13:40 +0200[diff] [blame]122 u-boot,dm-pre-reloc;
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]123 };
124
Marek Vasut36f83d92017-09-12 23:01:51 +0200[diff] [blame^]125 /*
126 * The external audio clocks are configured as 0 Hz fixed frequency
127 * clocks by default.
128 * Boards that provide audio clocks should override them.
129 */
130 audio_clk_a: audio_clk_a {
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 clock-frequency = <0>;
134 };
135
136 audio_clk_b: audio_clk_b {
137 compatible = "fixed-clock";
138 #clock-cells = <0>;
139 clock-frequency = <0>;
140 };
141
142 audio_clk_c: audio_clk_c {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <0>;
146 };
147
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]148 /* External CAN clock - to be overridden by boards that provide it */
149 can_clk: can {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <0>;
153 };
154
155 /* External SCIF clock - to be overridden by boards that provide it */
156 scif_clk: scif {
157 compatible = "fixed-clock";
158 #clock-cells = <0>;
159 clock-frequency = <0>;
160 };
161
Marek Vasut36f83d92017-09-12 23:01:51 +0200[diff] [blame^]162 /* External PCIe clock - can be overridden by the board */
163 pcie_bus_clk: pcie_bus {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <0>;
167 };
168
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]169 soc {
170 compatible = "simple-bus";
171 interrupt-parent = <&gic>;
172 #address-cells = <2>;
173 #size-cells = <2>;
174 ranges;
Marek Vasut7c084002017-08-20 17:13:40 +0200[diff] [blame]175 u-boot,dm-pre-reloc;
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]176
177 gic: interrupt-controller@f1010000 {
178 compatible = "arm,gic-400";
179 #interrupt-cells = <3>;
180 #address-cells = <0>;
181 interrupt-controller;
182 reg = <0x0 0xf1010000 0 0x1000>,
183 <0x0 0xf1020000 0 0x20000>,
184 <0x0 0xf1040000 0 0x20000>,
185 <0x0 0xf1060000 0 0x20000>;
186 interrupts = <GIC_PPI 9
187 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
188 clocks = <&cpg CPG_MOD 408>;
189 clock-names = "clk";
190 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
191 resets = <&cpg 408>;
192 };
193
194 timer {
195 compatible = "arm,armv8-timer";
196 interrupts = <GIC_PPI 13
197 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
198 <GIC_PPI 14
199 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
200 <GIC_PPI 11
201 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
202 <GIC_PPI 10
203 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
204 };
205
206 wdt0: watchdog@e6020000 {
207 compatible = "renesas,r8a7796-wdt",
208 "renesas,rcar-gen3-wdt";
209 reg = <0 0xe6020000 0 0x0c>;
210 clocks = <&cpg CPG_MOD 402>;
211 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
212 resets = <&cpg 402>;
213 status = "disabled";
214 };
215
216 gpio0: gpio@e6050000 {
217 compatible = "renesas,gpio-r8a7796",
218 "renesas,gpio-rcar";
219 reg = <0 0xe6050000 0 0x50>;
220 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
221 #gpio-cells = <2>;
222 gpio-controller;
223 gpio-ranges = <&pfc 0 0 16>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
226 clocks = <&cpg CPG_MOD 912>;
227 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
228 resets = <&cpg 912>;
229 };
230
231 gpio1: gpio@e6051000 {
232 compatible = "renesas,gpio-r8a7796",
233 "renesas,gpio-rcar";
234 reg = <0 0xe6051000 0 0x50>;
235 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
236 #gpio-cells = <2>;
237 gpio-controller;
238 gpio-ranges = <&pfc 0 32 29>;
239 #interrupt-cells = <2>;
240 interrupt-controller;
241 clocks = <&cpg CPG_MOD 911>;
242 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
243 resets = <&cpg 911>;
244 };
245
246 gpio2: gpio@e6052000 {
247 compatible = "renesas,gpio-r8a7796",
248 "renesas,gpio-rcar";
249 reg = <0 0xe6052000 0 0x50>;
250 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
251 #gpio-cells = <2>;
252 gpio-controller;
253 gpio-ranges = <&pfc 0 64 15>;
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 clocks = <&cpg CPG_MOD 910>;
257 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
258 resets = <&cpg 910>;
259 };
260
261 gpio3: gpio@e6053000 {
262 compatible = "renesas,gpio-r8a7796",
263 "renesas,gpio-rcar";
264 reg = <0 0xe6053000 0 0x50>;
265 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
266 #gpio-cells = <2>;
267 gpio-controller;
268 gpio-ranges = <&pfc 0 96 16>;
269 #interrupt-cells = <2>;
270 interrupt-controller;
271 clocks = <&cpg CPG_MOD 909>;
272 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
273 resets = <&cpg 909>;
274 };
275
276 gpio4: gpio@e6054000 {
277 compatible = "renesas,gpio-r8a7796",
278 "renesas,gpio-rcar";
279 reg = <0 0xe6054000 0 0x50>;
280 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
281 #gpio-cells = <2>;
282 gpio-controller;
283 gpio-ranges = <&pfc 0 128 18>;
284 #interrupt-cells = <2>;
285 interrupt-controller;
286 clocks = <&cpg CPG_MOD 908>;
287 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
288 resets = <&cpg 908>;
289 };
290
291 gpio5: gpio@e6055000 {
292 compatible = "renesas,gpio-r8a7796",
293 "renesas,gpio-rcar";
294 reg = <0 0xe6055000 0 0x50>;
295 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
296 #gpio-cells = <2>;
297 gpio-controller;
298 gpio-ranges = <&pfc 0 160 26>;
299 #interrupt-cells = <2>;
300 interrupt-controller;
301 clocks = <&cpg CPG_MOD 907>;
302 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
303 resets = <&cpg 907>;
304 };
305
306 gpio6: gpio@e6055400 {
307 compatible = "renesas,gpio-r8a7796",
308 "renesas,gpio-rcar";
309 reg = <0 0xe6055400 0 0x50>;
310 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
311 #gpio-cells = <2>;
312 gpio-controller;
313 gpio-ranges = <&pfc 0 192 32>;
314 #interrupt-cells = <2>;
315 interrupt-controller;
316 clocks = <&cpg CPG_MOD 906>;
317 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
318 resets = <&cpg 906>;
319 };
320
321 gpio7: gpio@e6055800 {
322 compatible = "renesas,gpio-r8a7796",
323 "renesas,gpio-rcar";
324 reg = <0 0xe6055800 0 0x50>;
325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
326 #gpio-cells = <2>;
327 gpio-controller;
328 gpio-ranges = <&pfc 0 224 4>;
329 #interrupt-cells = <2>;
330 interrupt-controller;
331 clocks = <&cpg CPG_MOD 905>;
332 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
333 resets = <&cpg 905>;
334 };
335
336 pfc: pin-controller@e6060000 {
337 compatible = "renesas,pfc-r8a7796";
338 reg = <0 0xe6060000 0 0x50c>;
339 };
340
341 pmu_a57 {
342 compatible = "arm,cortex-a57-pmu";
343 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-affinity = <&a57_0>,
346 <&a57_1>;
347 };
348
349 pmu_a53 {
350 compatible = "arm,cortex-a53-pmu";
351 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-affinity = <&a53_0>,
356 <&a53_1>,
357 <&a53_2>,
358 <&a53_3>;
359 };
360
361 cpg: clock-controller@e6150000 {
362 compatible = "renesas,r8a7796-cpg-mssr";
363 reg = <0 0xe6150000 0 0x1000>;
364 clocks = <&extal_clk>, <&extalr_clk>;
365 clock-names = "extal", "extalr";
366 #clock-cells = <2>;
367 #power-domain-cells = <0>;
368 #reset-cells = <1>;
Marek Vasut7c084002017-08-20 17:13:40 +0200[diff] [blame]369 u-boot,dm-pre-reloc;
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]370 };
371
372 rst: reset-controller@e6160000 {
373 compatible = "renesas,r8a7796-rst";
374 reg = <0 0xe6160000 0 0x0200>;
375 };
376
377 prr: chipid@fff00044 {
378 compatible = "renesas,prr";
379 reg = <0 0xfff00044 0 4>;
380 };
381
382 sysc: system-controller@e6180000 {
383 compatible = "renesas,r8a7796-sysc";
384 reg = <0 0xe6180000 0 0x0400>;
385 #power-domain-cells = <1>;
386 };
387
388 i2c_dvfs: i2c@e60b0000 {
389 #address-cells = <1>;
390 #size-cells = <0>;
391 compatible = "renesas,iic-r8a7796",
392 "renesas,rcar-gen3-iic",
393 "renesas,rmobile-iic";
394 reg = <0 0xe60b0000 0 0x425>;
395 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cpg CPG_MOD 926>;
397 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
398 resets = <&cpg 926>;
Marek Vasut36f83d92017-09-12 23:01:51 +0200[diff] [blame^]399 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
400 dma-names = "tx", "rx";
401 status = "disabled";
402 };
403
404 pwm0: pwm@e6e30000 {
405 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
406 reg = <0 0xe6e30000 0 8>;
407 #pwm-cells = <2>;
408 clocks = <&cpg CPG_MOD 523>;
409 resets = <&cpg 523>;
410 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
411 status = "disabled";
412 };
413
414 pwm1: pwm@e6e31000 {
415 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
416 reg = <0 0xe6e31000 0 8>;
417 #pwm-cells = <2>;
418 clocks = <&cpg CPG_MOD 523>;
419 resets = <&cpg 523>;
420 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
421 status = "disabled";
422 };
423
424 pwm2: pwm@e6e32000 {
425 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
426 reg = <0 0xe6e32000 0 8>;
427 #pwm-cells = <2>;
428 clocks = <&cpg CPG_MOD 523>;
429 resets = <&cpg 523>;
430 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 status = "disabled";
432 };
433
434 pwm3: pwm@e6e33000 {
435 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
436 reg = <0 0xe6e33000 0 8>;
437 #pwm-cells = <2>;
438 clocks = <&cpg CPG_MOD 523>;
439 resets = <&cpg 523>;
440 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
441 status = "disabled";
442 };
443
444 pwm4: pwm@e6e34000 {
445 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
446 reg = <0 0xe6e34000 0 8>;
447 #pwm-cells = <2>;
448 clocks = <&cpg CPG_MOD 523>;
449 resets = <&cpg 523>;
450 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
451 status = "disabled";
452 };
453
454 pwm5: pwm@e6e35000 {
455 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
456 reg = <0 0xe6e35000 0 8>;
457 #pwm-cells = <2>;
458 clocks = <&cpg CPG_MOD 523>;
459 resets = <&cpg 523>;
460 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
461 status = "disabled";
462 };
463
464 pwm6: pwm@e6e36000 {
465 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
466 reg = <0 0xe6e36000 0 8>;
467 #pwm-cells = <2>;
468 clocks = <&cpg CPG_MOD 523>;
469 resets = <&cpg 523>;
470 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]471 status = "disabled";
472 };
473
474 i2c0: i2c@e6500000 {
475 #address-cells = <1>;
476 #size-cells = <0>;
477 compatible = "renesas,i2c-r8a7796",
478 "renesas,rcar-gen3-i2c";
479 reg = <0 0xe6500000 0 0x40>;
480 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cpg CPG_MOD 931>;
482 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
483 resets = <&cpg 931>;
484 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
485 <&dmac2 0x91>, <&dmac2 0x90>;
486 dma-names = "tx", "rx", "tx", "rx";
487 i2c-scl-internal-delay-ns = <110>;
488 status = "disabled";
489 };
490
491 i2c1: i2c@e6508000 {
492 #address-cells = <1>;
493 #size-cells = <0>;
494 compatible = "renesas,i2c-r8a7796",
495 "renesas,rcar-gen3-i2c";
496 reg = <0 0xe6508000 0 0x40>;
497 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 930>;
499 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
500 resets = <&cpg 930>;
501 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
502 <&dmac2 0x93>, <&dmac2 0x92>;
503 dma-names = "tx", "rx", "tx", "rx";
504 i2c-scl-internal-delay-ns = <6>;
505 status = "disabled";
506 };
507
508 i2c2: i2c@e6510000 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 compatible = "renesas,i2c-r8a7796",
512 "renesas,rcar-gen3-i2c";
513 reg = <0 0xe6510000 0 0x40>;
514 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cpg CPG_MOD 929>;
516 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
517 resets = <&cpg 929>;
518 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
519 <&dmac2 0x95>, <&dmac2 0x94>;
520 dma-names = "tx", "rx", "tx", "rx";
521 i2c-scl-internal-delay-ns = <6>;
522 status = "disabled";
523 };
524
525 i2c3: i2c@e66d0000 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "renesas,i2c-r8a7796",
529 "renesas,rcar-gen3-i2c";
530 reg = <0 0xe66d0000 0 0x40>;
531 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cpg CPG_MOD 928>;
533 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
534 resets = <&cpg 928>;
535 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
536 dma-names = "tx", "rx";
537 i2c-scl-internal-delay-ns = <110>;
538 status = "disabled";
539 };
540
541 i2c4: i2c@e66d8000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "renesas,i2c-r8a7796",
545 "renesas,rcar-gen3-i2c";
546 reg = <0 0xe66d8000 0 0x40>;
547 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cpg CPG_MOD 927>;
549 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
550 resets = <&cpg 927>;
551 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
552 dma-names = "tx", "rx";
553 i2c-scl-internal-delay-ns = <110>;
554 status = "disabled";
555 };
556
557 i2c5: i2c@e66e0000 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 compatible = "renesas,i2c-r8a7796",
561 "renesas,rcar-gen3-i2c";
562 reg = <0 0xe66e0000 0 0x40>;
563 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&cpg CPG_MOD 919>;
565 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
566 resets = <&cpg 919>;
567 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
568 dma-names = "tx", "rx";
569 i2c-scl-internal-delay-ns = <110>;
570 status = "disabled";
571 };
572
573 i2c6: i2c@e66e8000 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "renesas,i2c-r8a7796",
577 "renesas,rcar-gen3-i2c";
578 reg = <0 0xe66e8000 0 0x40>;
579 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cpg CPG_MOD 918>;
581 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
582 resets = <&cpg 918>;
583 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
584 dma-names = "tx", "rx";
585 i2c-scl-internal-delay-ns = <6>;
586 status = "disabled";
587 };
588
589 can0: can@e6c30000 {
590 compatible = "renesas,can-r8a7796",
591 "renesas,rcar-gen3-can";
592 reg = <0 0xe6c30000 0 0x1000>;
593 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&cpg CPG_MOD 916>,
595 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
596 <&can_clk>;
597 clock-names = "clkp1", "clkp2", "can_clk";
598 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
599 assigned-clock-rates = <40000000>;
600 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
601 resets = <&cpg 916>;
602 status = "disabled";
603 };
604
605 can1: can@e6c38000 {
606 compatible = "renesas,can-r8a7796",
607 "renesas,rcar-gen3-can";
608 reg = <0 0xe6c38000 0 0x1000>;
609 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cpg CPG_MOD 915>,
611 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
612 <&can_clk>;
613 clock-names = "clkp1", "clkp2", "can_clk";
614 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
615 assigned-clock-rates = <40000000>;
616 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
617 resets = <&cpg 915>;
618 status = "disabled";
619 };
620
621 canfd: can@e66c0000 {
622 compatible = "renesas,r8a7796-canfd",
623 "renesas,rcar-gen3-canfd";
624 reg = <0 0xe66c0000 0 0x8000>;
625 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&cpg CPG_MOD 914>,
628 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
629 <&can_clk>;
630 clock-names = "fck", "canfd", "can_clk";
631 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
632 assigned-clock-rates = <40000000>;
633 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
634 resets = <&cpg 914>;
635 status = "disabled";
636
637 channel0 {
638 status = "disabled";
639 };
640
641 channel1 {
642 status = "disabled";
643 };
644 };
645
646 avb: ethernet@e6800000 {
647 compatible = "renesas,etheravb-r8a7796",
648 "renesas,etheravb-rcar-gen3";
649 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
650 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
675 interrupt-names = "ch0", "ch1", "ch2", "ch3",
676 "ch4", "ch5", "ch6", "ch7",
677 "ch8", "ch9", "ch10", "ch11",
678 "ch12", "ch13", "ch14", "ch15",
679 "ch16", "ch17", "ch18", "ch19",
680 "ch20", "ch21", "ch22", "ch23",
681 "ch24";
682 clocks = <&cpg CPG_MOD 812>;
683 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
684 resets = <&cpg 812>;
685 phy-mode = "rgmii-txid";
686 #address-cells = <1>;
687 #size-cells = <0>;
688 status = "disabled";
689 };
690
691 hscif0: serial@e6540000 {
692 compatible = "renesas,hscif-r8a7796",
693 "renesas,rcar-gen3-hscif",
694 "renesas,hscif";
695 reg = <0 0xe6540000 0 0x60>;
696 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cpg CPG_MOD 520>,
698 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
699 <&scif_clk>;
700 clock-names = "fck", "brg_int", "scif_clk";
701 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
702 <&dmac2 0x31>, <&dmac2 0x30>;
703 dma-names = "tx", "rx", "tx", "rx";
704 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
705 resets = <&cpg 520>;
706 status = "disabled";
707 };
708
709 hscif1: serial@e6550000 {
710 compatible = "renesas,hscif-r8a7796",
711 "renesas,rcar-gen3-hscif",
712 "renesas,hscif";
713 reg = <0 0xe6550000 0 0x60>;
714 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cpg CPG_MOD 519>,
716 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
717 <&scif_clk>;
718 clock-names = "fck", "brg_int", "scif_clk";
719 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
720 <&dmac2 0x33>, <&dmac2 0x32>;
721 dma-names = "tx", "rx", "tx", "rx";
722 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
723 resets = <&cpg 519>;
724 status = "disabled";
725 };
726
727 hscif2: serial@e6560000 {
728 compatible = "renesas,hscif-r8a7796",
729 "renesas,rcar-gen3-hscif",
730 "renesas,hscif";
731 reg = <0 0xe6560000 0 0x60>;
732 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&cpg CPG_MOD 518>,
734 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
735 <&scif_clk>;
736 clock-names = "fck", "brg_int", "scif_clk";
737 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
738 <&dmac2 0x35>, <&dmac2 0x34>;
739 dma-names = "tx", "rx", "tx", "rx";
740 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
741 resets = <&cpg 518>;
742 status = "disabled";
743 };
744
745 hscif3: serial@e66a0000 {
746 compatible = "renesas,hscif-r8a7796",
747 "renesas,rcar-gen3-hscif",
748 "renesas,hscif";
749 reg = <0 0xe66a0000 0 0x60>;
750 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&cpg CPG_MOD 517>,
752 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
753 <&scif_clk>;
754 clock-names = "fck", "brg_int", "scif_clk";
755 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
756 dma-names = "tx", "rx";
757 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
758 resets = <&cpg 517>;
759 status = "disabled";
760 };
761
762 hscif4: serial@e66b0000 {
763 compatible = "renesas,hscif-r8a7796",
764 "renesas,rcar-gen3-hscif",
765 "renesas,hscif";
766 reg = <0 0xe66b0000 0 0x60>;
767 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cpg CPG_MOD 516>,
769 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
770 <&scif_clk>;
771 clock-names = "fck", "brg_int", "scif_clk";
772 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
773 dma-names = "tx", "rx";
774 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
775 resets = <&cpg 516>;
776 status = "disabled";
777 };
778
779 scif0: serial@e6e60000 {
780 compatible = "renesas,scif-r8a7796",
781 "renesas,rcar-gen3-scif", "renesas,scif";
782 reg = <0 0xe6e60000 0 64>;
783 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cpg CPG_MOD 207>,
785 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
786 <&scif_clk>;
787 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
789 <&dmac2 0x51>, <&dmac2 0x50>;
790 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
792 resets = <&cpg 207>;
793 status = "disabled";
794 };
795
796 scif1: serial@e6e68000 {
797 compatible = "renesas,scif-r8a7796",
798 "renesas,rcar-gen3-scif", "renesas,scif";
799 reg = <0 0xe6e68000 0 64>;
800 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cpg CPG_MOD 206>,
802 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
803 <&scif_clk>;
804 clock-names = "fck", "brg_int", "scif_clk";
805 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
806 <&dmac2 0x53>, <&dmac2 0x52>;
807 dma-names = "tx", "rx", "tx", "rx";
808 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
809 resets = <&cpg 206>;
810 status = "disabled";
811 };
812
813 scif2: serial@e6e88000 {
814 compatible = "renesas,scif-r8a7796",
815 "renesas,rcar-gen3-scif", "renesas,scif";
816 reg = <0 0xe6e88000 0 64>;
817 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&cpg CPG_MOD 310>,
819 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
820 <&scif_clk>;
821 clock-names = "fck", "brg_int", "scif_clk";
822 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
823 resets = <&cpg 310>;
824 status = "disabled";
825 };
826
827 scif3: serial@e6c50000 {
828 compatible = "renesas,scif-r8a7796",
829 "renesas,rcar-gen3-scif", "renesas,scif";
830 reg = <0 0xe6c50000 0 64>;
831 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&cpg CPG_MOD 204>,
833 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
834 <&scif_clk>;
835 clock-names = "fck", "brg_int", "scif_clk";
836 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
837 dma-names = "tx", "rx";
838 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
839 resets = <&cpg 204>;
840 status = "disabled";
841 };
842
843 scif4: serial@e6c40000 {
844 compatible = "renesas,scif-r8a7796",
845 "renesas,rcar-gen3-scif", "renesas,scif";
846 reg = <0 0xe6c40000 0 64>;
847 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cpg CPG_MOD 203>,
849 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
850 <&scif_clk>;
851 clock-names = "fck", "brg_int", "scif_clk";
852 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
853 dma-names = "tx", "rx";
854 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
855 resets = <&cpg 203>;
856 status = "disabled";
857 };
858
859 scif5: serial@e6f30000 {
860 compatible = "renesas,scif-r8a7796",
861 "renesas,rcar-gen3-scif", "renesas,scif";
862 reg = <0 0xe6f30000 0 64>;
863 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&cpg CPG_MOD 202>,
865 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
866 <&scif_clk>;
867 clock-names = "fck", "brg_int", "scif_clk";
868 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
869 <&dmac2 0x5b>, <&dmac2 0x5a>;
870 dma-names = "tx", "rx", "tx", "rx";
871 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
872 resets = <&cpg 202>;
873 status = "disabled";
874 };
875
876 msiof0: spi@e6e90000 {
877 compatible = "renesas,msiof-r8a7796",
878 "renesas,rcar-gen3-msiof";
879 reg = <0 0xe6e90000 0 0x0064>;
880 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&cpg CPG_MOD 211>;
882 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
883 <&dmac2 0x41>, <&dmac2 0x40>;
884 dma-names = "tx", "rx";
885 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
886 resets = <&cpg 211>;
887 #address-cells = <1>;
888 #size-cells = <0>;
889 status = "disabled";
890 };
891
892 msiof1: spi@e6ea0000 {
893 compatible = "renesas,msiof-r8a7796",
894 "renesas,rcar-gen3-msiof";
895 reg = <0 0xe6ea0000 0 0x0064>;
896 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&cpg CPG_MOD 210>;
898 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
899 <&dmac2 0x43>, <&dmac2 0x42>;
900 dma-names = "tx", "rx";
901 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
902 resets = <&cpg 210>;
903 #address-cells = <1>;
904 #size-cells = <0>;
905 status = "disabled";
906 };
907
908 msiof2: spi@e6c00000 {
909 compatible = "renesas,msiof-r8a7796",
910 "renesas,rcar-gen3-msiof";
911 reg = <0 0xe6c00000 0 0x0064>;
912 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&cpg CPG_MOD 209>;
914 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
915 dma-names = "tx", "rx";
916 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
917 resets = <&cpg 209>;
918 #address-cells = <1>;
919 #size-cells = <0>;
920 status = "disabled";
921 };
922
923 msiof3: spi@e6c10000 {
924 compatible = "renesas,msiof-r8a7796",
925 "renesas,rcar-gen3-msiof";
926 reg = <0 0xe6c10000 0 0x0064>;
927 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&cpg CPG_MOD 208>;
929 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
930 dma-names = "tx", "rx";
931 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
932 resets = <&cpg 208>;
933 #address-cells = <1>;
934 #size-cells = <0>;
935 status = "disabled";
936 };
937
938 dmac0: dma-controller@e6700000 {
939 compatible = "renesas,dmac-r8a7796",
940 "renesas,rcar-dmac";
941 reg = <0 0xe6700000 0 0x10000>;
942 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
943 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
944 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
945 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
946 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
947 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
948 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
949 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
950 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
951 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
952 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
953 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
954 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
955 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
956 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
957 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
958 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "error",
960 "ch0", "ch1", "ch2", "ch3",
961 "ch4", "ch5", "ch6", "ch7",
962 "ch8", "ch9", "ch10", "ch11",
963 "ch12", "ch13", "ch14", "ch15";
964 clocks = <&cpg CPG_MOD 219>;
965 clock-names = "fck";
966 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
967 resets = <&cpg 219>;
968 #dma-cells = <1>;
969 dma-channels = <16>;
970 };
971
972 dmac1: dma-controller@e7300000 {
973 compatible = "renesas,dmac-r8a7796",
974 "renesas,rcar-dmac";
975 reg = <0 0xe7300000 0 0x10000>;
976 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
977 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
978 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
979 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
980 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
981 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
982 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
983 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
984 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
985 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
986 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
987 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
988 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
989 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
990 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
991 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
992 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "error",
994 "ch0", "ch1", "ch2", "ch3",
995 "ch4", "ch5", "ch6", "ch7",
996 "ch8", "ch9", "ch10", "ch11",
997 "ch12", "ch13", "ch14", "ch15";
998 clocks = <&cpg CPG_MOD 218>;
999 clock-names = "fck";
1000 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1001 resets = <&cpg 218>;
1002 #dma-cells = <1>;
1003 dma-channels = <16>;
1004 };
1005
1006 dmac2: dma-controller@e7310000 {
1007 compatible = "renesas,dmac-r8a7796",
1008 "renesas,rcar-dmac";
1009 reg = <0 0xe7310000 0 0x10000>;
1010 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
1011 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
1012 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
1013 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
1014 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
1015 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
1016 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
1017 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
1018 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
1019 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
1020 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
1021 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
1022 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
1023 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
1024 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
1025 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
1026 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1027 interrupt-names = "error",
1028 "ch0", "ch1", "ch2", "ch3",
1029 "ch4", "ch5", "ch6", "ch7",
1030 "ch8", "ch9", "ch10", "ch11",
1031 "ch12", "ch13", "ch14", "ch15";
1032 clocks = <&cpg CPG_MOD 217>;
1033 clock-names = "fck";
1034 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1035 resets = <&cpg 217>;
1036 #dma-cells = <1>;
1037 dma-channels = <16>;
1038 };
1039
Marek Vasut36f83d92017-09-12 23:01:51 +0200[diff] [blame^]1040 audma0: dma-controller@ec700000 {
1041 compatible = "renesas,dmac-r8a7796",
1042 "renesas,rcar-dmac";
1043 reg = <0 0xec700000 0 0x10000>;
1044 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1045 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1046 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1047 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1048 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1049 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1050 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1051 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1052 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1053 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1054 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1055 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1056 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1057 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1058 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1059 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1060 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1061 interrupt-names = "error",
1062 "ch0", "ch1", "ch2", "ch3",
1063 "ch4", "ch5", "ch6", "ch7",
1064 "ch8", "ch9", "ch10", "ch11",
1065 "ch12", "ch13", "ch14", "ch15";
1066 clocks = <&cpg CPG_MOD 502>;
1067 clock-names = "fck";
1068 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1069 resets = <&cpg 502>;
1070 #dma-cells = <1>;
1071 dma-channels = <16>;
1072 };
1073
1074 audma1: dma-controller@ec720000 {
1075 compatible = "renesas,dmac-r8a7796",
1076 "renesas,rcar-dmac";
1077 reg = <0 0xec720000 0 0x10000>;
1078 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
1079 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1080 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
1081 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
1082 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
1083 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
1084 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1085 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1086 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1087 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1088 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
1089 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1090 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1091 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
1092 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
1093 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
1094 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
1095 interrupt-names = "error",
1096 "ch0", "ch1", "ch2", "ch3",
1097 "ch4", "ch5", "ch6", "ch7",
1098 "ch8", "ch9", "ch10", "ch11",
1099 "ch12", "ch13", "ch14", "ch15";
1100 clocks = <&cpg CPG_MOD 501>;
1101 clock-names = "fck";
1102 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1103 resets = <&cpg 501>;
1104 #dma-cells = <1>;
1105 dma-channels = <16>;
1106 };
1107
1108 hsusb: usb@e6590000 {
1109 /* placeholder */
1110 };
1111
1112 xhci0: usb@ee000000 {
1113 /* placeholder */
1114 };
1115
1116 ohci0: usb@ee080000 {
1117 /* placeholder */
1118 };
1119
1120 ehci0: usb@ee080100 {
1121 /* placeholder */
1122 };
1123
1124 usb2_phy0: usb-phy@ee080200 {
1125 /* placeholder */
1126 };
1127
1128 ohci1: usb@ee0a0000 {
1129 /* placeholder */
1130 };
1131
1132 ehci1: usb@ee0a0100 {
1133 /* placeholder */
1134 };
1135
1136 usb2_phy1: usb-phy@ee0a0200 {
1137 /* placeholder */
1138 };
1139
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]1140 sdhi0: sd@ee100000 {
1141 compatible = "renesas,sdhi-r8a7796";
1142 reg = <0 0xee100000 0 0x2000>;
1143 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&cpg CPG_MOD 314>;
1145 max-frequency = <200000000>;
1146 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1147 resets = <&cpg 314>;
1148 status = "disabled";
1149 };
1150
1151 sdhi1: sd@ee120000 {
1152 compatible = "renesas,sdhi-r8a7796";
1153 reg = <0 0xee120000 0 0x2000>;
1154 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1155 clocks = <&cpg CPG_MOD 313>;
1156 max-frequency = <200000000>;
1157 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1158 resets = <&cpg 313>;
1159 status = "disabled";
1160 };
1161
1162 sdhi2: sd@ee140000 {
1163 compatible = "renesas,sdhi-r8a7796";
1164 reg = <0 0xee140000 0 0x2000>;
1165 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&cpg CPG_MOD 312>;
1167 max-frequency = <200000000>;
1168 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1169 resets = <&cpg 312>;
1170 status = "disabled";
1171 };
1172
1173 sdhi3: sd@ee160000 {
1174 compatible = "renesas,sdhi-r8a7796";
1175 reg = <0 0xee160000 0 0x2000>;
1176 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MOD 311>;
1178 max-frequency = <200000000>;
1179 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1180 resets = <&cpg 311>;
1181 status = "disabled";
1182 };
1183
1184 tsc: thermal@e6198000 {
1185 compatible = "renesas,r8a7796-thermal";
1186 reg = <0 0xe6198000 0 0x68>,
1187 <0 0xe61a0000 0 0x5c>,
1188 <0 0xe61a8000 0 0x5c>;
1189 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&cpg CPG_MOD 522>;
1193 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1194 resets = <&cpg 522>;
1195 #thermal-sensor-cells = <1>;
1196 status = "okay";
1197 };
1198
1199 thermal-zones {
1200 sensor_thermal1: sensor-thermal1 {
1201 polling-delay-passive = <250>;
1202 polling-delay = <1000>;
1203 thermal-sensors = <&tsc 0>;
1204
1205 trips {
1206 sensor1_crit: sensor1-crit {
1207 temperature = <120000>;
1208 hysteresis = <2000>;
1209 type = "critical";
1210 };
1211 };
1212 };
1213
1214 sensor_thermal2: sensor-thermal2 {
1215 polling-delay-passive = <250>;
1216 polling-delay = <1000>;
1217 thermal-sensors = <&tsc 1>;
1218
1219 trips {
1220 sensor2_crit: sensor2-crit {
1221 temperature = <120000>;
1222 hysteresis = <2000>;
1223 type = "critical";
1224 };
1225 };
1226 };
1227
1228 sensor_thermal3: sensor-thermal3 {
1229 polling-delay-passive = <250>;
1230 polling-delay = <1000>;
1231 thermal-sensors = <&tsc 2>;
1232
1233 trips {
1234 sensor3_crit: sensor3-crit {
1235 temperature = <120000>;
1236 hysteresis = <2000>;
1237 type = "critical";
1238 };
1239 };
1240 };
1241 };
Marek Vasut36f83d92017-09-12 23:01:51 +0200[diff] [blame^]1242
1243 rcar_sound: sound@ec500000 {
1244 /*
1245 * #sound-dai-cells is required
1246 *
1247 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1248 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1249 */
1250 /*
1251 * #clock-cells is required for audio_clkout0/1/2/3
1252 *
1253 * clkout : #clock-cells = <0>; <&rcar_sound>;
1254 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1255 */
1256 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1257 reg = <0 0xec500000 0 0x1000>, /* SCU */
1258 <0 0xec5a0000 0 0x100>, /* ADG */
1259 <0 0xec540000 0 0x1000>, /* SSIU */
1260 <0 0xec541000 0 0x280>, /* SSI */
1261 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1262 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1263
1264 clocks = <&cpg CPG_MOD 1005>,
1265 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1266 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1267 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1268 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1269 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1270 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1271 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1272 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1273 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1274 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1275 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1276 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1277 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1278 <&audio_clk_a>, <&audio_clk_b>,
1279 <&audio_clk_c>,
1280 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
1281 clock-names = "ssi-all",
1282 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1283 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1284 "ssi.1", "ssi.0",
1285 "src.9", "src.8", "src.7", "src.6",
1286 "src.5", "src.4", "src.3", "src.2",
1287 "src.1", "src.0",
1288 "mix.1", "mix.0",
1289 "ctu.1", "ctu.0",
1290 "dvc.0", "dvc.1",
1291 "clk_a", "clk_b", "clk_c", "clk_i";
1292 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1293 resets = <&cpg 1005>,
1294 <&cpg 1006>, <&cpg 1007>,
1295 <&cpg 1008>, <&cpg 1009>,
1296 <&cpg 1010>, <&cpg 1011>,
1297 <&cpg 1012>, <&cpg 1013>,
1298 <&cpg 1014>, <&cpg 1015>;
1299 reset-names = "ssi-all",
1300 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1301 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1302 "ssi.1", "ssi.0";
1303 status = "disabled";
1304
1305 rcar_sound,dvc {
1306 dvc0: dvc-0 {
1307 dmas = <&audma1 0xbc>;
1308 dma-names = "tx";
1309 };
1310 dvc1: dvc-1 {
1311 dmas = <&audma1 0xbe>;
1312 dma-names = "tx";
1313 };
1314 };
1315
1316 rcar_sound,mix {
1317 mix0: mix-0 { };
1318 mix1: mix-1 { };
1319 };
1320
1321 rcar_sound,ctu {
1322 ctu00: ctu-0 { };
1323 ctu01: ctu-1 { };
1324 ctu02: ctu-2 { };
1325 ctu03: ctu-3 { };
1326 ctu10: ctu-4 { };
1327 ctu11: ctu-5 { };
1328 ctu12: ctu-6 { };
1329 ctu13: ctu-7 { };
1330 };
1331
1332 rcar_sound,src {
1333 src0: src-0 {
1334 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1335 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1336 dma-names = "rx", "tx";
1337 };
1338 src1: src-1 {
1339 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1340 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1341 dma-names = "rx", "tx";
1342 };
1343 src2: src-2 {
1344 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1345 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1346 dma-names = "rx", "tx";
1347 };
1348 src3: src-3 {
1349 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1350 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1351 dma-names = "rx", "tx";
1352 };
1353 src4: src-4 {
1354 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1355 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1356 dma-names = "rx", "tx";
1357 };
1358 src5: src-5 {
1359 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1360 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1361 dma-names = "rx", "tx";
1362 };
1363 src6: src-6 {
1364 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1365 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1366 dma-names = "rx", "tx";
1367 };
1368 src7: src-7 {
1369 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1370 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1371 dma-names = "rx", "tx";
1372 };
1373 src8: src-8 {
1374 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1375 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1376 dma-names = "rx", "tx";
1377 };
1378 src9: src-9 {
1379 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1380 dmas = <&audma0 0x97>, <&audma1 0xba>;
1381 dma-names = "rx", "tx";
1382 };
1383 };
1384
1385 rcar_sound,ssi {
1386 ssi0: ssi-0 {
1387 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1388 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1389 dma-names = "rx", "tx", "rxu", "txu";
1390 };
1391 ssi1: ssi-1 {
1392 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1393 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1394 dma-names = "rx", "tx", "rxu", "txu";
1395 };
1396 ssi2: ssi-2 {
1397 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1398 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1399 dma-names = "rx", "tx", "rxu", "txu";
1400 };
1401 ssi3: ssi-3 {
1402 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1403 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1404 dma-names = "rx", "tx", "rxu", "txu";
1405 };
1406 ssi4: ssi-4 {
1407 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1408 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1409 dma-names = "rx", "tx", "rxu", "txu";
1410 };
1411 ssi5: ssi-5 {
1412 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1413 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1414 dma-names = "rx", "tx", "rxu", "txu";
1415 };
1416 ssi6: ssi-6 {
1417 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1418 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1419 dma-names = "rx", "tx", "rxu", "txu";
1420 };
1421 ssi7: ssi-7 {
1422 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1423 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1424 dma-names = "rx", "tx", "rxu", "txu";
1425 };
1426 ssi8: ssi-8 {
1427 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1428 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1429 dma-names = "rx", "tx", "rxu", "txu";
1430 };
1431 ssi9: ssi-9 {
1432 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1433 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1434 dma-names = "rx", "tx", "rxu", "txu";
1435 };
1436 };
1437 };
1438
1439 pciec0: pcie@fe000000 {
1440 /* placeholder */
1441 };
1442
1443 pciec1: pcie@ee800000 {
1444 /* placeholder */
1445 };
1446
1447 du: display@feb00000 {
1448 /* placeholder */
1449
1450 ports {
1451 #address-cells = <1>;
1452 #size-cells = <0>;
1453
1454 port@0 {
1455 reg = <0>;
1456 du_out_rgb: endpoint {
1457 };
1458 };
1459 };
1460 };
Marek Vasutb938f382017-07-21 23:16:59 +0200[diff] [blame]1461 };
1462};