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git01.mediatek.com / filogic / uboot / 36c8fe0f354b1f28b3f76f15145bb6064cd2aace / . / arch / arm / dts / imx6ul-kontron-bl-common.dtsi
blob: a6cf0f21c66d12aa0b7549984fd0a4af1c9eb6c2 [file] [log] [blame]
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017 exceet electronics GmbH
4 * Copyright (C) 2018 Kontron Electronics GmbH
5 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 gpio-leds {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
15
16 led1 {
17 label = "debug-led1";
18 gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
19 default-state = "off";
20 linux,default-trigger = "heartbeat";
21 };
22
23 led2 {
24 label = "debug-led2";
25 gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
26 default-state = "off";
27 };
28
29 led3 {
30 label = "debug-led3";
31 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
32 default-state = "off";
33 };
34 };
35
36 pwm-beeper {
37 compatible = "pwm-beeper";
38 pwms = <&pwm8 0 5000>;
39 };
40
41 reg_3v3: regulator-3v3 {
42 compatible = "regulator-fixed";
43 regulator-name = "3v3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
47
48 reg_5v: regulator-5v {
49 compatible = "regulator-fixed";
50 regulator-name = "5v";
51 regulator-min-microvolt = <5000000>;
52 regulator-max-microvolt = <5000000>;
53 };
54
55 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
56 compatible = "regulator-fixed";
57 regulator-name = "usb_otg1_vbus";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
60 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
61 enable-active-high;
62 };
63
64 reg_vref_adc: regulator-vref-adc {
65 compatible = "regulator-fixed";
66 regulator-name = "vref-adc";
67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <3300000>;
69 };
70};
71
72&adc1 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_adc1>;
75 num-channels = <3>;
76 vref-supply = <&reg_vref_adc>;
77 status = "okay";
78};
79
80&can2 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_flexcan2>;
83 status = "okay";
84};
85
86&ecspi1 {
Marcel Ziswiler64e36c12022-07-21 15:27:30 +0200[diff] [blame]87 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_ecspi1>;
90 status = "okay";
91
92 eeprom@0 {
93 compatible = "anvo,anv32e61w", "atmel,at25";
94 reg = <0>;
95 spi-max-frequency = <20000000>;
96 spi-cpha;
97 spi-cpol;
98 pagesize = <1>;
99 size = <8192>;
100 address-width = <16>;
101 };
102};
103
104&fec1 {
105 pinctrl-0 = <&pinctrl_enet1>;
106 /delete-node/ mdio;
107};
108
109&fec2 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
112 phy-mode = "rmii";
113 phy-handle = <&ethphy2>;
114 status = "okay";
115
116 mdio {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 ethphy1: ethernet-phy@1 {
121 reg = <1>;
122 micrel,led-mode = <0>;
123 clocks = <&clks IMX6UL_CLK_ENET_REF>;
124 clock-names = "rmii-ref";
125 };
126
127 ethphy2: ethernet-phy@2 {
128 reg = <2>;
129 micrel,led-mode = <0>;
130 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
131 clock-names = "rmii-ref";
132 };
133 };
134};
135
136&i2c1 {
137 clock-frequency = <100000>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c1>;
140 status = "okay";
141};
142
143&i2c4 {
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c4>;
147 status = "okay";
148
149 rtc@32 {
150 compatible = "epson,rx8900";
151 reg = <0x32>;
152 };
153};
154
155&pwm8 {
Marcel Ziswiler64e36c12022-07-21 15:27:30 +0200[diff] [blame]156 #pwm-cells = <2>;
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_pwm8>;
159 status = "okay";
160};
161
162&uart1 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_uart1>;
165 status = "okay";
166};
167
168&uart2 {
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_uart2>;
171 linux,rs485-enabled-at-boot-time;
172 rs485-rx-during-tx;
173 rs485-rts-active-low;
174 uart-has-rtscts;
175 status = "okay";
176};
177
178&uart3 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3>;
Marcel Ziswiler64e36c12022-07-21 15:27:30 +0200[diff] [blame]181 uart-has-rtscts;
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]182 status = "okay";
183};
184
185&uart4 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart4>;
188 status = "okay";
189};
190
191&usbotg1 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_usbotg1>;
194 dr_mode = "otg";
195 srp-disable;
196 hnp-disable;
197 adp-disable;
198 over-current-active-low;
199 vbus-supply = <&reg_usb_otg1_vbus>;
200 status = "okay";
201};
202
203&usbotg2 {
204 dr_mode = "host";
205 disable-over-current;
206 vbus-supply = <&reg_5v>;
207 status = "okay";
208};
209
210&usdhc1 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_usdhc1>;
213 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
214 keep-power-in-suspend;
215 wakeup-source;
216 vmmc-supply = <&reg_3v3>;
217 voltage-ranges = <3300 3300>;
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]218 no-1-8-v;
219 status = "okay";
220};
221
222&usdhc2 {
223 pinctrl-names = "default", "state_100mhz", "state_200mhz";
224 pinctrl-0 = <&pinctrl_usdhc2>;
225 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
226 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
227 non-removable;
228 keep-power-in-suspend;
229 wakeup-source;
230 vmmc-supply = <&reg_3v3>;
231 voltage-ranges = <3300 3300>;
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]232 no-1-8-v;
233 status = "okay";
234};
235
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]236&iomuxc {
237 pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
238
239 pinctrl_adc1: adc1grp {
240 fsl,pins = <
241 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
242 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
243 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
244 >;
245 };
246
247 pinctrl_ecspi1: ecspi1grp {
248 fsl,pins = <
249 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
250 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
251 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
252 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
253 >;
254 };
255
256 pinctrl_enet2: enet2grp {
257 fsl,pins = <
258 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
259 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
260 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
261 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
262 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
263 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
264 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
265 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
266 >;
267 };
268
269 pinctrl_enet2_mdio: enet2mdiogrp {
270 fsl,pins = <
271 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
272 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
273 >;
274 };
275
276 pinctrl_flexcan2: flexcan2grp{
277 fsl,pins = <
278 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
279 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
280 >;
281 };
282
283 pinctrl_gpio: gpiogrp {
284 fsl,pins = <
285 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
286 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
287 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
288 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
289 >;
290 };
291
292 pinctrl_gpio_leds: gpioledsgrp {
293 fsl,pins = <
294 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
295 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
296 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
297 >;
298 };
299
300 pinctrl_i2c1: i2c1grp {
301 fsl,pins = <
302 MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
303 MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
304 >;
305 };
306
307 pinctrl_i2c4: i2c4grp {
308 fsl,pins = <
309 MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
310 MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
311 >;
312 };
313
314 pinctrl_pwm8: pwm8grp {
315 fsl,pins = <
316 MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
317 >;
318 };
319
320 pinctrl_uart1: uart1grp {
321 fsl,pins = <
322 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
323 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
324 >;
325 };
326
327 pinctrl_uart2: uart2grp {
328 fsl,pins = <
329 MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
330 MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
331 MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
332 /*
333 * mux unused RTS to make sure it doesn't cause
334 * any interrupts when it is undefined
335 */
336 MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
337 >;
338 };
339
340 pinctrl_uart3: uart3grp {
341 fsl,pins = <
342 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
343 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
344 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
345 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
346 >;
347 };
348
349 pinctrl_uart4: uart4grp {
350 fsl,pins = <
351 MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
352 MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
353 >;
354 };
355
356 pinctrl_usbotg1: usbotg1 {
357 fsl,pins = <
358 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
359 >;
360 };
361
362 pinctrl_usdhc1: usdhc1grp {
363 fsl,pins = <
364 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
365 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
366 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
367 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
368 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
369 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
370 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
371 >;
372 };
373
374 pinctrl_usdhc2: usdhc2grp {
375 fsl,pins = <
376 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
377 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
378 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
379 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
380 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
381 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
382 >;
383 };
384
385 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
386 fsl,pins = <
387 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
388 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
389 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
390 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
391 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
392 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
393 >;
394 };
395
396 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
397 fsl,pins = <
398 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
399 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
400 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
401 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
402 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
403 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
404 >;
405 };
Frieder Schrempfc6d170b2021-09-29 16:42:41 +0200[diff] [blame]406};