Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 36af3d3c73e31a232f7bd860fbec9a5288dc6113 / . / configs / chromebook_jerry_defconfig
blob: 8688abba425994833bcba9111721f760ebc6ee3d [file] [log] [blame]
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
5CONFIG_TARGET_CHROMEBOOK_JERRY=y
Simon Glass94906e42016-01-21 19:45:17 -0700[diff] [blame]6CONFIG_ROCKCHIP_FAST_SPL=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]8CONFIG_DM_KEYBOARD=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
10CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]11CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]12CONFIG_HUSH_PARSER=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]13CONFIG_CMD_BOOTZ=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]14# CONFIG_CMD_IMLS is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]15CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]16CONFIG_CMD_SF=y
17CONFIG_CMD_SPI=y
18CONFIG_CMD_I2C=y
19CONFIG_CMD_GPIO=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]20# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]21CONFIG_CMD_DHCP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]22CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]23CONFIG_CMD_PING=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]24CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]25CONFIG_CMD_TIME=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]26CONFIG_CMD_PMIC=y
27CONFIG_CMD_REGULATOR=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]28CONFIG_CMD_EXT2=y
29CONFIG_CMD_EXT4=y
30CONFIG_CMD_FAT=y
31CONFIG_CMD_FS_GENERIC=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]32CONFIG_SPL_OF_CONTROL=y
Simon Glass8d32f4b2016-01-21 19:43:38 -0700[diff] [blame]33CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]34CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]35CONFIG_SPL_REGMAP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]36CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]37CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]38# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]39CONFIG_CLK=y
40CONFIG_SPL_CLK=y
41CONFIG_ROCKCHIP_GPIO=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]42CONFIG_I2C_CROS_EC_TUNNEL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]43CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]44CONFIG_I2C_MUX=y
45CONFIG_CROS_EC_KEYB=y
46CONFIG_CMD_CROS_EC=y
47CONFIG_CROS_EC=y
48CONFIG_CROS_EC_SPI=y
Simon Glassaf0b7442016-01-21 19:43:36 -0700[diff] [blame]49CONFIG_PWRSEQ=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]50CONFIG_ROCKCHIP_DWMMC=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]51CONFIG_PINCTRL=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]52CONFIG_SPL_PINCTRL=y
Simon Glass2ac46482015-12-29 05:22:45 -0700[diff] [blame]53# CONFIG_SPL_PINCTRL_FULL is not set
Heiko Stübner66bd8d32016-07-16 00:17:13 +0200[diff] [blame]54CONFIG_ROCKCHIP_RK3288_PINCTRL=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]55CONFIG_DM_PMIC=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]56# CONFIG_SPL_PMIC_CHILDREN is not set
Simon Glass99ac7012016-01-21 19:43:48 -0700[diff] [blame]57CONFIG_PMIC_RK808=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]58CONFIG_DM_REGULATOR=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]59CONFIG_DM_REGULATOR_FIXED=y
Simon Glass99ac7012016-01-21 19:43:48 -0700[diff] [blame]60CONFIG_REGULATOR_RK808=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]61CONFIG_DM_PWM=y
62CONFIG_PWM_ROCKCHIP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]63CONFIG_RAM=y
64CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]65CONFIG_DEBUG_UART=y
66CONFIG_DEBUG_UART_BASE=0xff690000
67CONFIG_DEBUG_UART_CLOCK=24000000
68CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]69CONFIG_SYS_NS16550=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]70CONFIG_ROCKCHIP_SPI=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]71CONFIG_SYSRESET=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]72CONFIG_DM_VIDEO=y
Anatolij Gustschin4601eb42016-01-25 17:17:22 +0100[diff] [blame]73CONFIG_DISPLAY=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]74CONFIG_VIDEO_ROCKCHIP=y
Simon Glass2ac46482015-12-29 05:22:45 -0700[diff] [blame]75CONFIG_USE_TINY_PRINTF=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]76CONFIG_CMD_DHRYSTONE=y
77CONFIG_ERRNO_STR=y