Marek Vasut | 92c3483 | 2011-01-19 04:40:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> |
| 3 | * |
| 4 | * (C) Copyright 2009 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Configuration settings for the MX51EVK Board |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __CONFIG_H |
| 25 | #define __CONFIG_H |
| 26 | |
| 27 | #include <config_cmd_default.h> |
| 28 | |
| 29 | /* |
| 30 | * High Level Board Configuration Options |
| 31 | */ |
| 32 | /* An i.MX51 CPU */ |
| 33 | #define CONFIG_MX51 |
| 34 | #include <asm/arch/imx-regs.h> |
| 35 | |
| 36 | #define CONFIG_SYS_MX5_HCLK 24000000 |
| 37 | #define CONFIG_SYS_MX5_CLK32 32768 |
| 38 | #define CONFIG_DISPLAY_CPUINFO |
| 39 | #define CONFIG_DISPLAY_BOARDINFO |
| 40 | |
Jana Rapava | 8b8ae20 | 2011-07-11 14:16:44 +0000 | [diff] [blame] | 41 | #define CONFIG_SYS_TEXT_BASE 0x97800000 |
| 42 | |
Marek Vasut | 92c3483 | 2011-01-19 04:40:37 +0000 | [diff] [blame] | 43 | /* |
| 44 | * Bootloader Components Configuration |
| 45 | */ |
| 46 | #define CONFIG_CMD_SPI |
| 47 | #define CONFIG_CMD_SF |
| 48 | #define CONFIG_CMD_MMC |
| 49 | #define CONFIG_CMD_FAT |
Marek Vasut | 175f31f | 2011-07-11 14:16:45 +0000 | [diff] [blame] | 50 | #define CONFIG_CMD_EXT2 |
Marek Vasut | 92c3483 | 2011-01-19 04:40:37 +0000 | [diff] [blame] | 51 | #define CONFIG_CMD_IDE |
| 52 | #undef CONFIG_CMD_IMLS |
| 53 | |
| 54 | /* |
| 55 | * Environmental settings |
| 56 | */ |
| 57 | |
| 58 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
| 59 | #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) |
| 60 | #define CONFIG_ENV_SIZE (4 * 1024) |
| 61 | |
| 62 | /* |
| 63 | * ATAG setup |
| 64 | */ |
| 65 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 66 | #define CONFIG_REVISION_TAG |
| 67 | #define CONFIG_SETUP_MEMORY_TAGS |
| 68 | #define CONFIG_INITRD_TAG |
| 69 | |
Grant Likely | 100b849 | 2011-03-28 09:59:07 +0000 | [diff] [blame] | 70 | #define CONFIG_OF_LIBFDT 1 |
| 71 | |
Marek Vasut | 92c3483 | 2011-01-19 04:40:37 +0000 | [diff] [blame] | 72 | /* |
| 73 | * Size of malloc() pool |
| 74 | */ |
| 75 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) |
| 76 | |
| 77 | #define CONFIG_BOARD_EARLY_INIT_F |
| 78 | #define BOARD_LATE_INIT |
| 79 | |
| 80 | /* |
| 81 | * Hardware drivers |
| 82 | */ |
| 83 | #define CONFIG_MXC_UART |
| 84 | #define CONFIG_SYS_MX51_UART1 |
| 85 | #define CONFIG_CONS_INDEX 1 |
| 86 | #define CONFIG_BAUDRATE 115200 |
| 87 | #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} |
| 88 | |
| 89 | #define CONFIG_MXC_GPIO |
| 90 | |
| 91 | /* |
| 92 | * SPI Interface |
| 93 | */ |
| 94 | #ifdef CONFIG_CMD_SPI |
| 95 | |
| 96 | #define CONFIG_HARD_SPI |
| 97 | #define CONFIG_MXC_SPI |
| 98 | #define CONFIG_DEFAULT_SPI_BUS 1 |
| 99 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
| 100 | |
| 101 | /* SPI FLASH */ |
| 102 | #ifdef CONFIG_CMD_SF |
| 103 | |
| 104 | #define CONFIG_SPI_FLASH |
| 105 | #define CONFIG_SPI_FLASH_SST |
| 106 | #define CONFIG_SPI_FLASH_CS (1 | 121 << 8) |
| 107 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) |
| 108 | #define CONFIG_SF_DEFAULT_SPEED 25000000 |
| 109 | |
| 110 | #define CONFIG_ENV_SPI_CS (1 | 121 << 8) |
| 111 | #define CONFIG_ENV_SPI_BUS 0 |
| 112 | #define CONFIG_ENV_SPI_MAX_HZ 25000000 |
| 113 | #define CONFIG_ENV_SPI_MODE (SPI_MODE_0) |
| 114 | #define CONFIG_FSL_ENV_IN_SF |
| 115 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 116 | #define CONFIG_SYS_NO_FLASH |
| 117 | |
| 118 | #else |
| 119 | #define CONFIG_ENV_IS_NOWHERE |
| 120 | #endif |
| 121 | |
| 122 | /* SPI PMIC */ |
| 123 | #define CONFIG_FSL_PMIC |
| 124 | #define CONFIG_FSL_PMIC_BUS 0 |
| 125 | #define CONFIG_FSL_PMIC_CS (0 | 120 << 8) |
| 126 | #define CONFIG_FSL_PMIC_CLK 25000000 |
| 127 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
| 128 | #define CONFIG_RTC_MC13783 |
| 129 | #endif |
| 130 | |
| 131 | /* |
| 132 | * MMC Configs |
| 133 | */ |
| 134 | #ifdef CONFIG_CMD_MMC |
| 135 | #define CONFIG_MMC |
| 136 | #define CONFIG_GENERIC_MMC |
| 137 | #define CONFIG_FSL_ESDHC |
| 138 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| 139 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 |
| 140 | #endif |
| 141 | |
| 142 | /* |
| 143 | * ATA/IDE |
| 144 | */ |
| 145 | #ifdef CONFIG_CMD_IDE |
| 146 | #define CONFIG_LBA48 |
| 147 | #undef CONFIG_IDE_LED |
| 148 | #undef CONFIG_IDE_RESET |
| 149 | |
| 150 | #define CONFIG_MX51_PATA |
| 151 | |
| 152 | #define __io |
| 153 | |
| 154 | #define CONFIG_SYS_IDE_MAXBUS 1 |
| 155 | #define CONFIG_SYS_IDE_MAXDEVICE 1 |
| 156 | |
| 157 | #define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000 |
| 158 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 |
| 159 | |
| 160 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xa0 |
| 161 | #define CONFIG_SYS_ATA_REG_OFFSET 0xa0 |
| 162 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xd8 |
| 163 | |
| 164 | #define CONFIG_SYS_ATA_STRIDE 4 |
| 165 | |
| 166 | #define CONFIG_IDE_PREINIT |
| 167 | #define CONFIG_MXC_ATA_PIO_MODE 4 |
| 168 | #endif |
| 169 | |
| 170 | /* |
| 171 | * Filesystems |
| 172 | */ |
| 173 | #ifdef CONFIG_CMD_FAT |
| 174 | #define CONFIG_DOS_PARTITION |
| 175 | #endif |
| 176 | |
| 177 | #undef CONFIG_CMD_PING |
| 178 | #undef CONFIG_CMD_DHCP |
| 179 | #undef CONFIG_CMD_NET |
| 180 | #undef CONFIG_CMD_NFS |
| 181 | #define CONFIG_CMD_DATE |
| 182 | |
| 183 | /* |
| 184 | * Miscellaneous configurable options |
| 185 | */ |
| 186 | #define CONFIG_ENV_OVERWRITE |
| 187 | #define CONFIG_BOOTDELAY 3 |
| 188 | #define CONFIG_LOADADDR 0x90800000 |
| 189 | |
| 190 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 191 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
| 192 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 193 | #define CONFIG_SYS_PROMPT "Efika> " |
| 194 | #define CONFIG_AUTO_COMPLETE |
| 195 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 196 | /* Print Buffer Size */ |
| 197 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 198 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 199 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 200 | |
| 201 | #define CONFIG_SYS_MEMTEST_START 0x90000000 |
| 202 | #define CONFIG_SYS_MEMTEST_END 0x10000 |
| 203 | |
| 204 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 205 | |
| 206 | #define CONFIG_SYS_HZ 1000 |
| 207 | #define CONFIG_CMDLINE_EDITING |
| 208 | |
| 209 | /*----------------------------------------------------------------------- |
| 210 | * Stack sizes |
| 211 | * |
| 212 | * The stack sizes are set up in start.S using the settings below |
| 213 | */ |
| 214 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ |
| 215 | |
| 216 | /*----------------------------------------------------------------------- |
| 217 | * Physical Memory Map |
| 218 | */ |
| 219 | #define CONFIG_NR_DRAM_BANKS 1 |
| 220 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
| 221 | #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) |
| 222 | |
| 223 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
| 224 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) |
| 225 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) |
| 226 | |
| 227 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 228 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 229 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 230 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 231 | |
| 232 | #define CONFIG_SYS_DDR_CLKSEL 0 |
| 233 | #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 |
| 234 | |
| 235 | #endif |