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git01.mediatek.com / filogic / uboot / 3672aa5efb00a6ea075cdce690e771203d645c29 / . / arch / arm / mach-rmobile / pfc-r8a7740.c
blob: 5d42a68266b14ceacc44e85ee218d4348ea1a644 [file] [log] [blame]
Nobuhiro Iwamatsu852a0a22012-07-20 13:07:43 +0900[diff] [blame]1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <common.h>
22#include <sh_pfc.h>
23#include <asm/gpio.h>
24#include <asm/arch/irqs.h>
25
26#define CPU_ALL_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
28 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
29 PORT_10(fn, pfx##20, sfx), \
30 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
31
32enum {
33 PINMUX_RESERVED = 0,
34
35 /* PORT0_DATA -> PORT211_DATA */
36 PINMUX_DATA_BEGIN,
37 PORT_ALL(DATA),
38 PINMUX_DATA_END,
39
40 /* PORT0_IN -> PORT211_IN */
41 PINMUX_INPUT_BEGIN,
42 PORT_ALL(IN),
43 PINMUX_INPUT_END,
44
45 /* PORT0_IN_PU -> PORT211_IN_PU */
46 PINMUX_INPUT_PULLUP_BEGIN,
47 PORT_ALL(IN_PU),
48 PINMUX_INPUT_PULLUP_END,
49
50 /* PORT0_IN_PD -> PORT211_IN_PD */
51 PINMUX_INPUT_PULLDOWN_BEGIN,
52 PORT_ALL(IN_PD),
53 PINMUX_INPUT_PULLDOWN_END,
54
55 /* PORT0_OUT -> PORT211_OUT */
56 PINMUX_OUTPUT_BEGIN,
57 PORT_ALL(OUT),
58 PINMUX_OUTPUT_END,
59
60 PINMUX_FUNCTION_BEGIN,
61 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
62 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
63 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
64 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
65 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
66 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
67 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
68 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
69 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
70 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
71
72 MSEL1CR_31_0, MSEL1CR_31_1,
73 MSEL1CR_30_0, MSEL1CR_30_1,
74 MSEL1CR_29_0, MSEL1CR_29_1,
75 MSEL1CR_28_0, MSEL1CR_28_1,
76 MSEL1CR_27_0, MSEL1CR_27_1,
77 MSEL1CR_26_0, MSEL1CR_26_1,
78 MSEL1CR_16_0, MSEL1CR_16_1,
79 MSEL1CR_15_0, MSEL1CR_15_1,
80 MSEL1CR_14_0, MSEL1CR_14_1,
81 MSEL1CR_13_0, MSEL1CR_13_1,
82 MSEL1CR_12_0, MSEL1CR_12_1,
83 MSEL1CR_9_0, MSEL1CR_9_1,
84 MSEL1CR_7_0, MSEL1CR_7_1,
85 MSEL1CR_6_0, MSEL1CR_6_1,
86 MSEL1CR_5_0, MSEL1CR_5_1,
87 MSEL1CR_4_0, MSEL1CR_4_1,
88 MSEL1CR_3_0, MSEL1CR_3_1,
89 MSEL1CR_2_0, MSEL1CR_2_1,
90 MSEL1CR_0_0, MSEL1CR_0_1,
91
92 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
93 MSEL3CR_6_0, MSEL3CR_6_1,
94
95 MSEL4CR_19_0, MSEL4CR_19_1,
96 MSEL4CR_18_0, MSEL4CR_18_1,
97 MSEL4CR_15_0, MSEL4CR_15_1,
98 MSEL4CR_10_0, MSEL4CR_10_1,
99 MSEL4CR_6_0, MSEL4CR_6_1,
100 MSEL4CR_4_0, MSEL4CR_4_1,
101 MSEL4CR_1_0, MSEL4CR_1_1,
102
103 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
104 MSEL5CR_30_0, MSEL5CR_30_1,
105 MSEL5CR_29_0, MSEL5CR_29_1,
106 MSEL5CR_27_0, MSEL5CR_27_1,
107 MSEL5CR_25_0, MSEL5CR_25_1,
108 MSEL5CR_23_0, MSEL5CR_23_1,
109 MSEL5CR_21_0, MSEL5CR_21_1,
110 MSEL5CR_19_0, MSEL5CR_19_1,
111 MSEL5CR_17_0, MSEL5CR_17_1,
112 MSEL5CR_15_0, MSEL5CR_15_1,
113 MSEL5CR_14_0, MSEL5CR_14_1,
114 MSEL5CR_13_0, MSEL5CR_13_1,
115 MSEL5CR_12_0, MSEL5CR_12_1,
116 MSEL5CR_11_0, MSEL5CR_11_1,
117 MSEL5CR_10_0, MSEL5CR_10_1,
118 MSEL5CR_8_0, MSEL5CR_8_1,
119 MSEL5CR_7_0, MSEL5CR_7_1,
120 MSEL5CR_6_0, MSEL5CR_6_1,
121 MSEL5CR_5_0, MSEL5CR_5_1,
122 MSEL5CR_4_0, MSEL5CR_4_1,
123 MSEL5CR_3_0, MSEL5CR_3_1,
124 MSEL5CR_2_0, MSEL5CR_2_1,
125 MSEL5CR_0_0, MSEL5CR_0_1,
126 PINMUX_FUNCTION_END,
127
128 PINMUX_MARK_BEGIN,
129
130 /* IRQ */
131 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
132 IRQ1_MARK,
133 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
134 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
135 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
136 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
137 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
138 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
139 IRQ8_MARK,
140 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
141 IRQ10_MARK,
142 IRQ11_MARK,
143 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
144 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
145 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
146 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
147 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
148 IRQ17_MARK,
149 IRQ18_MARK,
150 IRQ19_MARK,
151 IRQ20_MARK,
152 IRQ21_MARK,
153 IRQ22_MARK,
154 IRQ23_MARK,
155 IRQ24_MARK,
156 IRQ25_MARK,
157 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
158 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
159 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
160 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
161 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
162 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
163
164 /* Function */
165
166 /* DBGT */
167 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
168 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
169 DBGMD21_MARK,
170
171 /* FSI */
172 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
173 FSIAISLD_PORT5_MARK,
174 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
175 FSIASPDIF_PORT18_MARK,
176 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
177 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
178 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
179
180 /* FMSI */
181 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
182 FMSISLD_PORT6_MARK,
183 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
184 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
185 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
186
187 /* SCIFA0 */
188 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
189 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
190
191 /* SCIFA1 */
192 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
193 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
194
195 /* SCIFA2 */
196 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
197 SCIFA2_SCK_PORT199_MARK,
198 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
199 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
200
201 /* SCIFA3 */
202 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
203 SCIFA3_SCK_PORT116_MARK,
204 SCIFA3_CTS_PORT117_MARK,
205 SCIFA3_RXD_PORT174_MARK,
206 SCIFA3_TXD_PORT175_MARK,
207
208 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
209 SCIFA3_SCK_PORT158_MARK,
210 SCIFA3_CTS_PORT162_MARK,
211 SCIFA3_RXD_PORT159_MARK,
212 SCIFA3_TXD_PORT160_MARK,
213
214 /* SCIFA4 */
215 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
216 SCIFA4_TXD_PORT13_MARK,
217
218 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
219 SCIFA4_TXD_PORT203_MARK,
220
221 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
222 SCIFA4_TXD_PORT93_MARK,
223
224 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
225 SCIFA4_SCK_PORT205_MARK,
226
227 /* SCIFA5 */
228 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
229 SCIFA5_RXD_PORT10_MARK,
230
231 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
232 SCIFA5_TXD_PORT208_MARK,
233
234 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
235 SCIFA5_RXD_PORT92_MARK,
236
237 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
238 SCIFA5_SCK_PORT206_MARK,
239
240 /* SCIFA6 */
241 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
242
243 /* SCIFA7 */
244 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
245
246 /* SCIFAB */
247 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
248 SCIFB_RXD_PORT191_MARK,
249 SCIFB_TXD_PORT192_MARK,
250 SCIFB_RTS_PORT186_MARK,
251 SCIFB_CTS_PORT187_MARK,
252
253 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
254 SCIFB_RXD_PORT3_MARK,
255 SCIFB_TXD_PORT4_MARK,
256 SCIFB_RTS_PORT172_MARK,
257 SCIFB_CTS_PORT173_MARK,
258
259 /* LCD0 */
260 LCDC0_SELECT_MARK,
261
262 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
263 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
264 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
265 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
266 LCD0_D16_MARK, LCD0_D17_MARK,
267 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
268 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
269 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
270 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
271 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
272
273 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
274 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
275 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
276 LCD0_LCLK_PORT165_MARK,
277
278 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
279 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
280 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
281 LCD0_LCLK_PORT102_MARK,
282
283 /* LCD1 */
284 LCDC1_SELECT_MARK,
285
286 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
287 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
288 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
289 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
290 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
291 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
292 LCD1_DON_MARK, LCD1_VCPWC_MARK,
293 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
294
295 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
296 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
297 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
298 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
299
300 /* RSPI */
301 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
302 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
303 RSPI_MISO_A_MARK,
304
305 /* VIO CKO */
306 VIO_CKO1_MARK, /* needs fixup */
307 VIO_CKO2_MARK,
308 VIO_CKO_1_MARK,
309 VIO_CKO_MARK,
310
311 /* VIO0 */
312 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
313 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
314 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
315 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
316 VIO0_FIELD_MARK,
317
318 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
319 VIO0_D14_PORT25_MARK,
320 VIO0_D15_PORT24_MARK,
321
322 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
323 VIO0_D14_PORT95_MARK,
324 VIO0_D15_PORT96_MARK,
325
326 /* VIO1 */
327 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
328 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
329 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
330
331 /* TPU0 */
332 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
333 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
334 TPU0TO2_PORT202_MARK,
335
336 /* SSP1 0 */
337 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
338 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
339 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
340
341 /* SSP1 1 */
342 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
343 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
344 STP1_IPSYNC_MARK,
345
346 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
347 STP1_IPEN_PORT187_MARK,
348
349 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
350 STP1_IPEN_PORT193_MARK,
351
352 /* SIM */
353 SIM_RST_MARK, SIM_CLK_MARK,
354 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
355 SIM_D_PORT199_MARK,
356
357 /* SDHI0 */
358 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
359 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
360
361 /* SDHI1 */
362 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
363 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
364
365 /* SDHI2 */
366 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
367 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
368
369 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
370 SDHI2_WP_PORT25_MARK,
371
372 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
373 SDHI2_CD_PORT202_MARK,
374
375 /* MSIOF2 */
376 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
377 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
378 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
379 MSIOF2_RSCK_MARK,
380
381 /* KEYSC */
382 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
383 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
384 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
385
386 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
387 KEYIN1_PORT44_MARK,
388 KEYIN2_PORT45_MARK,
389 KEYIN3_PORT46_MARK,
390
391 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
392 KEYIN1_PORT57_MARK,
393 KEYIN2_PORT56_MARK,
394 KEYIN3_PORT55_MARK,
395
396 /* VOU */
397 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
398 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
399 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
400 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
401 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
402
403 /* MEMC */
404 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
405 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
406 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
407 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
408 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
409
410 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
411 MEMC_ADV_MARK,
412 MEMC_WAIT_MARK,
413 MEMC_BUSCLK_MARK,
414
415 MEMC_A1_MARK, /* MSEL4CR_6_1 */
416 MEMC_DREQ0_MARK,
417 MEMC_DREQ1_MARK,
418 MEMC_A0_MARK,
419
420 /* MMC */
421 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
422 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
423 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
424 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
425
426 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
427 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
428 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
429 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
430
431 /* MSIOF0 */
432 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
433 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
434 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
435 MSIOF0_TSYNC_MARK,
436
437 /* MSIOF1 */
438 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
439 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
440
441 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
442 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
443 MSIOF1_TSYNC_PORT120_MARK,
444 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
445
446 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
447 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
448 MSIOF1_RXD_PORT75_MARK,
449 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
453
454 /* USB0 */
455 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
456
457 /* USB1 */
458 USB1_OCI_MARK, USB1_PPON_MARK,
459
460 /* BBIF1 */
461 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
462 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
463 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
464
465 /* BBIF2 */
466 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
467 BBIF2_RXD2_PORT60_MARK,
468 BBIF2_TSYNC2_PORT6_MARK,
469 BBIF2_TSCK2_PORT59_MARK,
470
471 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
472 BBIF2_TXD2_PORT183_MARK,
473 BBIF2_TSCK2_PORT89_MARK,
474 BBIF2_TSYNC2_PORT184_MARK,
475
476 /* BSC / FLCTL / PCMCIA */
477 CS0_MARK, CS2_MARK, CS4_MARK,
478 CS5B_MARK, CS6A_MARK,
479 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
480 CS5A_PORT19_MARK,
481 IOIS16_MARK, /* ? */
482
483 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
484 A4_FOE_MARK, /* share with FLCTL */
485 A5_FCDE_MARK, /* share with FLCTL */
486 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
487 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
488 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
489 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
490 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
491 A26_MARK,
492
493 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
494 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
495 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
496 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
497 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
498 D15_NAF15_MARK, /* share with FLCTL */
499 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
500 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
501 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
502 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
503
504 WE0_FWE_MARK, /* share with FLCTL */
505 WE1_MARK,
506 WE2_ICIORD_MARK, /* share with PCMCIA */
507 WE3_ICIOWR_MARK, /* share with PCMCIA */
508 CKO_MARK, BS_MARK, RDWR_MARK,
509 RD_FSC_MARK, /* share with FLCTL */
510 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
511 WAIT_PORT90_MARK,
512
513 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
514
515 /* IRDA */
516 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
517
518 /* ATAPI */
519 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
520 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
521 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
522 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
523 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
524 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
525 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
526 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
527
528 /* RMII */
529 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
530 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
531 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
532 RMII_REF50CK_MARK, /* for RMII */
533 RMII_REF125CK_MARK, /* for GMII */
534
535 /* GEther */
536 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
537 ET_ETXD2_MARK, ET_ETXD3_MARK,
538 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
539 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
540 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
541 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
542 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
543 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
544 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
545 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
546
547 /* DMA0 */
548 DREQ0_MARK, DACK0_MARK,
549
550 /* DMA1 */
551 DREQ1_MARK, DACK1_MARK,
552
553 /* SYSC */
554 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
555
556 /* IRREM */
557 IROUT_MARK,
558
559 /* SDENC */
560 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
561
562 /* DEBUG */
563 EDEBGREQ_PULLUP_MARK, /* for JTAG */
564 EDEBGREQ_PULLDOWN_MARK,
565
566 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
567 TRACEAUD_FROM_LCDC0_MARK,
568 TRACEAUD_FROM_MEMC_MARK,
569
570 PINMUX_MARK_END,
571};
572
573static unsigned short pinmux_data[] = {
574 /* specify valid pin states for each pin in GPIO mode */
575
576 /* I/O and Pull U/D */
577 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
578 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
579 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
580 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
581 PORT_DATA_IO(8), PORT_DATA_IO(9),
582
583 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
584 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
585 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
586 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
587 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
588
589 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
590 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
591 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
592 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
593 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
594
595 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
596 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
597 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
598 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
599 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
600
601 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
602 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
603 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
604 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
605 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
606
607 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
608 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
609 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
610 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
611 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
612
613 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
614 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
615 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
616 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
617 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
618
619 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
620 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
621 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
622 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
623 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
624
625 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
626 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
627 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
628 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
629 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
630
631 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
632 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
633 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
634 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
635 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
636
637 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
638 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
639 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
640 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
641 PORT_DATA_IO(108), PORT_DATA_IO(109),
642
643 PORT_DATA_IO(110), PORT_DATA_IO(111),
644 PORT_DATA_IO(112), PORT_DATA_IO(113),
645 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
646 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
647 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
648
649 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
650 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
651 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
652 PORT_DATA_IO(126), PORT_DATA_IO(127),
653 PORT_DATA_IO(128), PORT_DATA_IO(129),
654
655 PORT_DATA_IO(130), PORT_DATA_IO(131),
656 PORT_DATA_IO(132), PORT_DATA_IO(133),
657 PORT_DATA_IO(134), PORT_DATA_IO(135),
658 PORT_DATA_IO(136), PORT_DATA_IO(137),
659 PORT_DATA_IO(138), PORT_DATA_IO(139),
660
661 PORT_DATA_IO(140), PORT_DATA_IO(141),
662 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
663 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
664 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
665 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
666
667 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
668 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
669 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
670 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
671 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
672
673 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
674 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
675 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
676 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
677 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
678
679 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
680 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
681 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
682 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
683 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
684
685 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
686 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
687 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
688 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
689 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
690
691 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
692 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
693 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
694 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
695 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
696
697 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
698 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
699 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
700 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
701 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
702
703 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
704
705 /* Port0 */
706 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
707 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
708 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
709 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
710 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
711 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
712 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
713
714 /* Port1 */
715 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
716 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
717 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
718 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
719 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
720 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
721 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
722
723 /* Port2 */
724 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
725 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
726 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
727 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
728 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
729
730 /* Port3 */
731 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
732 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
733 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
734 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
735
736 /* Port4 */
737 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
738 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
739 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
740 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
741
742 /* Port5 */
743 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
744 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
745 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
746 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
747 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
748
749 /* Port6 */
750 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
751 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
752 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
753 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
754 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
755
756 /* Port7 */
757 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
758
759 /* Port8 */
760 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
761
762 /* Port9 */
763 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
764 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
765
766 /* Port10 */
767 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
768 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0,
769 MSEL5CR_15_0),
770 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
771
772 /* Port11 */
773 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
774 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
775
776 /* Port12 */
777 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
778 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0,
779 MSEL5CR_11_0),
780 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
781 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
782 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
783
784 /* Port13 */
785 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
786 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0,
787 MSEL5CR_11_0),
788 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
789 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
790
791 /* Port14 */
792 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
793 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
794 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
795 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
796 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
797
798 /* Port15 */
799 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
800 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
801 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
802 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
803 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
804
805 /* Port16 */
806 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
807 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
808
809 /* Port17 */
810 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
811 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
812
813 /* Port18 */
814 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
815 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
816
817 /* Port19 */
818 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
819 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
820 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
821
822 /* Port20 */
823 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
824 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0,
825 MSEL5CR_14_0),
826 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
827
828 /* Port21 */
829 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
830 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
831 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
832 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
833 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
834 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
835
836 /* Port22 */
837 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
838 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
839 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
840
841 /* Port23 */
842 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
843 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
844 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
845 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
846 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
847 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
848
849 /* Port24 */
850 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
851 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
852 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
853 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
854
855 /* Port25 */
856 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
857 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
858 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
859 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
860
861 /* Port26 */
862 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
863 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
864 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
865
866 /* Port27 - Port39 Function */
867 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
868 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
869 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
870 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
871 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
872 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
873 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
874 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
875 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
876 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
877 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
878 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
879 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
880
881 /* Port38 IRQ */
882 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
883
884 /* Port40 */
885 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
886 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
887 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
888
889 /* Port41 */
890 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
891 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
892 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
893
894 /* Port42 */
895 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
896 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
897 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
898
899 /* Port43 */
900 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
901 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
902 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
903 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
904
905 /* Port44 */
906 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
907 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
908 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
909 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
910
911 /* Port45 */
912 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
913 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
914 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
915 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
916
917 /* Port46 */
918 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
919 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
920 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
921
922 /* Port47 */
923 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
924 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
925 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
926
927 /* Port48 */
928 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
929 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
930 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
931
932 /* Port49 */
933 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
934 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
935 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
936 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
937
938 /* Port50 */
939 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
940 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
941 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
942 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
943
944 /* Port51 */
945 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
946 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
947 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
948
949 /* Port52 */
950 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
951 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
952 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
953
954 /* Port53 */
955 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
956 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
957 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
958
959 /* Port54 */
960 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
961 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
962 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
963
964 /* Port55 */
965 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
966 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
967 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
968 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
969
970 /* Port56 */
971 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
972 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
973 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
974 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
975 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
976
977 /* Port57 */
978 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
979 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
980 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
981 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
982 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
983
984 /* Port58 */
985 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
986 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
987 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
988 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
989 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
990
991 /* Port59 */
992 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
993 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
994 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
995
996 /* Port60 */
997 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
998 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
999 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
1000
1001 /* Port61 */
1002 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
1003 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1004
1005 /* Port62 */
1006 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1007 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1008 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1009 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1010
1011 /* Port63 */
1012 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1013 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1014 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1015
1016 /* Port64 */
1017 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1018 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1019 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1020 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1021
1022 /* Port65 */
1023 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1024 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1025 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1026
1027 /* Port66 */
1028 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1029 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1030 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1031 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1032
1033 /* Port67 - Port73 Function1 */
1034 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1035 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1036 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1037 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1038 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1039 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1040 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1041
1042 /* Port67 - Port73 Function2 */
1043 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1044 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1045 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1046 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1047 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1048 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1049 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1050
1051 /* Port67 - Port73 Function4 */
1052 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1053 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1054 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1055 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1056 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1057 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1058 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1059
1060 /* Port67 - Port73 Function6 */
1061 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1062 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1063 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1064 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1065 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1066 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1067 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1068
1069 /* Port67 - Port71 IRQ */
1070 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1071 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1072 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1073 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1074 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1075
1076 /* Port74 */
1077 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1078 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1079 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1080 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1081 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1082
1083 /* Port75 */
1084 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1085 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1086 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1087 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1088 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1089
1090 /* Port76 - Port80 Function */
1091 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1092 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1093 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1094 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1095 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1096
1097 /* Port81 */
1098 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1099 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1100
1101 /* Port82 - Port88 Function */
1102 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1103 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1104 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1105 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1106 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1107 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1108 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1109
1110 /* Port89 */
1111 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1112 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1113 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1114
1115 /* Port90 */
1116 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1117 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1118 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1119 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1120
1121 /* Port91 */
1122 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1123 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1124 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1,
1125 MSEL5CR_14_0),
1126 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1127
1128 /* Port92 */
1129 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1130 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1131 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1,
1132 MSEL5CR_14_0),
1133 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1134 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1135
1136 /* Port93 */
1137 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1138 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1139 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1,
1140 MSEL5CR_11_0),
1141 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1142 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1143
1144 /* Port94 */
1145 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1146 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1147 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1,
1148 MSEL5CR_11_0),
1149 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1150 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1151
1152 /* Port95 */
1153 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1154 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1155
1156 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1157 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1158 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1159 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1160
1161 /* Port96 */
1162 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1163 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1164
1165 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1166 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1167 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1168 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1169
1170 /* Port97 */
1171 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1172 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1173 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1174 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1175 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1176
1177 /* Port98 */
1178 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1179 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1180 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1181 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1182
1183 /* Port99 */
1184 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1185 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1186 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1187 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1188 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1189
1190 /* Port100 */
1191 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1192 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1193 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1194 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1195
1196 /* Port101 */
1197 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1198
1199 /* Port102 */
1200 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1201 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1202
1203 /* Port103 */
1204 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1205 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1206 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1207
1208 /* Port104 */
1209 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1210 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1211 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1212
1213 /* Port105 */
1214 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1215 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1216
1217 /* Port106 */
1218 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1219 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1220
1221 /* Port107 - Port115 Function */
1222 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1223 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1224 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1225 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1226 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1227 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1228 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1229 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1230 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1231
1232 /* Port116 */
1233 PINMUX_DATA(A25_MARK, PORT116_FN1),
1234 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1235 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1236 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1237 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1238
1239 /* Port117 */
1240 PINMUX_DATA(A24_MARK, PORT117_FN1),
1241 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1242 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1243 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1244 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1245
1246 /* Port118 */
1247 PINMUX_DATA(A23_MARK, PORT118_FN1),
1248 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1249 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1250 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1251 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1252
1253 /* Port119 */
1254 PINMUX_DATA(A22_MARK, PORT119_FN1),
1255 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1256 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1257 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1258 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1259
1260 /* Port120 */
1261 PINMUX_DATA(A21_MARK, PORT120_FN1),
1262 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1263 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1264 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
1265
1266 /* Port121 */
1267 PINMUX_DATA(A20_MARK, PORT121_FN1),
1268 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1269 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1270 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1271
1272 /* Port122 */
1273 PINMUX_DATA(A19_MARK, PORT122_FN1),
1274 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1275
1276 /* Port123 */
1277 PINMUX_DATA(A18_MARK, PORT123_FN1),
1278 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1279
1280 /* Port124 */
1281 PINMUX_DATA(A17_MARK, PORT124_FN1),
1282 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1283
1284 /* Port125 - Port141 Function */
1285 PINMUX_DATA(A16_MARK, PORT125_FN1),
1286 PINMUX_DATA(A15_MARK, PORT126_FN1),
1287 PINMUX_DATA(A14_MARK, PORT127_FN1),
1288 PINMUX_DATA(A13_MARK, PORT128_FN1),
1289 PINMUX_DATA(A12_MARK, PORT129_FN1),
1290 PINMUX_DATA(A11_MARK, PORT130_FN1),
1291 PINMUX_DATA(A10_MARK, PORT131_FN1),
1292 PINMUX_DATA(A9_MARK, PORT132_FN1),
1293 PINMUX_DATA(A8_MARK, PORT133_FN1),
1294 PINMUX_DATA(A7_MARK, PORT134_FN1),
1295 PINMUX_DATA(A6_MARK, PORT135_FN1),
1296 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1297 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1298 PINMUX_DATA(A3_MARK, PORT138_FN1),
1299 PINMUX_DATA(A2_MARK, PORT139_FN1),
1300 PINMUX_DATA(A1_MARK, PORT140_FN1),
1301 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1302
1303 /* Port142 - Port157 Function1 */
1304 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1305 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1306 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1307 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1308 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1309 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1310 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1311 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1312 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1313 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1314 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1315 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1316 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1317 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1318 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1319 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1320
1321 /* Port142 - Port149 Function3 */
1322 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1323 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1324 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1325 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1326 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1327 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1328 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1329 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1330
1331 /* Port158 */
1332 PINMUX_DATA(D31_MARK, PORT158_FN1),
1333 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1334 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1335 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1336 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1337 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1338
1339 /* Port159 */
1340 PINMUX_DATA(D30_MARK, PORT159_FN1),
1341 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1342 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1343 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1344 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1345
1346 /* Port160 */
1347 PINMUX_DATA(D29_MARK, PORT160_FN1),
1348 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1349 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1350 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1351 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1352
1353 /* Port161 */
1354 PINMUX_DATA(D28_MARK, PORT161_FN1),
1355 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1356 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1357 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1358 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1359 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1360
1361 /* Port162 */
1362 PINMUX_DATA(D27_MARK, PORT162_FN1),
1363 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1364 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1365 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1366 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1367
1368 /* Port163 */
1369 PINMUX_DATA(D26_MARK, PORT163_FN1),
1370 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1371 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1372 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1373 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1374 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1375
1376 /* Port164 */
1377 PINMUX_DATA(D25_MARK, PORT164_FN1),
1378 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1379 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1380 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1381 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1382
1383 /* Port165 */
1384 PINMUX_DATA(D24_MARK, PORT165_FN1),
1385 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1386 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1387 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1388
1389 /* Port166 - Port171 Function1 */
1390 PINMUX_DATA(D21_MARK, PORT166_FN1),
1391 PINMUX_DATA(D20_MARK, PORT167_FN1),
1392 PINMUX_DATA(D19_MARK, PORT168_FN1),
1393 PINMUX_DATA(D18_MARK, PORT169_FN1),
1394 PINMUX_DATA(D17_MARK, PORT170_FN1),
1395 PINMUX_DATA(D16_MARK, PORT171_FN1),
1396
1397 /* Port166 - Port171 Function3 */
1398 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1399 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1400 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1401 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1402 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1403 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1404
1405 /* Port166 - Port171 Function6 */
1406 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1407 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1408 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1409 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1410 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1411 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1412
1413 /* Port167 - Port171 IRQ */
1414 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1415 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1416 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1417 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1418 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1419
1420 /* Port172 */
1421 PINMUX_DATA(D23_MARK, PORT172_FN1),
1422 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1423 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1424 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1425 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1426
1427 /* Port173 */
1428 PINMUX_DATA(D22_MARK, PORT173_FN1),
1429 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1430 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1431 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1432 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1433
1434 /* Port174 */
1435 PINMUX_DATA(A26_MARK, PORT174_FN1),
1436 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1437 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1438 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1439
1440 /* Port175 */
1441 PINMUX_DATA(A0_MARK, PORT175_FN1),
1442 PINMUX_DATA(BS_MARK, PORT175_FN2),
1443 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1444 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1445
1446 /* Port176 */
1447 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1448
1449 /* Port177 */
1450 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1451 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1452 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1453 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1454
1455 /* Port178 */
1456 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1457 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1458 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1459
1460 /* Port179 */
1461 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1462 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1463 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1464
1465 /* Port180 */
1466 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1467 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1468 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1469 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1470 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1471
1472 /* Port181 */
1473 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1474 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1475 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1476
1477 /* Port182 */
1478 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1479 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1480 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1481
1482 /* Port183 */
1483 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1484 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1485 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1486
1487 /* Port184 */
1488 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1489 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1490 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1491
1492 /* Port185 - Port192 Function1 */
1493 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1494 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1495 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1496 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1497 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1498 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1499 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1500
1501 /* Port185 - Port192 Function3 */
1502 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1503 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1504 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1505 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1506 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1507 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1508 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1509 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1510
1511 /* Port185 - Port192 Function6 */
1512 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1513 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1514 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1515 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1516 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1517 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1518 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1519 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1520
1521 /* Port193 */
1522 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1523 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1524 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1),
1525 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1526
1527 /* Port194 */
1528 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1529 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1530 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1),
1531 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1532
1533 /* Port195 */
1534 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1535 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1536 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1537 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1538
1539 /* Port196 */
1540 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1541 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1542 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1543 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1544
1545 /* Port197 */
1546 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1547 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1548 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1549 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1550
1551 /* Port198 */
1552 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1553 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1554 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1555 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1556
1557 /* Port199 */
1558 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1559 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1560 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1561 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1562 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1563 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1564
1565 /* Port200 */
1566 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1567 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1568 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1569 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1570 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1571
1572 /* Port201 */
1573 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1574 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1575
1576 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1577 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1578 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1579 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1580
1581 /* Port202 */
1582 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1583 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1584
1585 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1586 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1587 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1588 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1589 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1590 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1591
1592 /* Port203 - Port208 Function1 */
1593 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1594 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1595 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1596 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1597 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1598 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1599
1600 /* Port203 - Port208 Function3 */
1601 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1602 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1603 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1604 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1605 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1606 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1607
1608 /* Port203 - Port208 Function6 */
1609 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1610 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1611 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1612 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1613 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1614 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1615
1616 /* Port203 - Port208 Function7 */
1617 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0,
1618 MSEL5CR_11_1),
1619 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0,
1620 MSEL5CR_11_1),
1621 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1622 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1623 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0,
1624 MSEL5CR_14_1),
1625 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0,
1626 MSEL5CR_14_1),
1627
1628 /* Port209 */
1629 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1630 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
1631
1632 /* Port210 */
1633 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1634
1635 /* Port211 */
1636 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1637
1638 /* LCDC select */
1639 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1640 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1641
1642 /* SDENC */
1643 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1644 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1645
1646 /* SYSC */
1647 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1648 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1649
1650 /* DEBUG */
1651 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1652 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1653
1654 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1655 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1656 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1657};
1658
1659static struct pinmux_gpio pinmux_gpios[] = {
1660
1661 /* PORT */
1662 GPIO_PORT_ALL(),
1663
1664 /* IRQ */
1665 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1666 GPIO_FN(IRQ1),
1667 GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
1668 GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
1669 GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
1670 GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
1671 GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
1672 GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
1673 GPIO_FN(IRQ8),
1674 GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
1675 GPIO_FN(IRQ10),
1676 GPIO_FN(IRQ11),
1677 GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
1678 GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
1679 GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
1680 GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
1681 GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
1682 GPIO_FN(IRQ17),
1683 GPIO_FN(IRQ18),
1684 GPIO_FN(IRQ19),
1685 GPIO_FN(IRQ20),
1686 GPIO_FN(IRQ21),
1687 GPIO_FN(IRQ22),
1688 GPIO_FN(IRQ23),
1689 GPIO_FN(IRQ24),
1690 GPIO_FN(IRQ25),
1691 GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
1692 GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
1693 GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
1694 GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
1695 GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
1696 GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
1697
1698 /* Function */
1699
1700 /* DBGT */
1701 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
1702 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
1703 GPIO_FN(DBGMD21),
1704
1705 /* FSI */
1706 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
1707 GPIO_FN(FSIAISLD_PORT5),
1708 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
1709 GPIO_FN(FSIASPDIF_PORT18),
1710 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
1711 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
1712 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
1713
1714 /* FMSI */
1715 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
1716 GPIO_FN(FMSISLD_PORT6),
1717 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
1718 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
1719 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
1720 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
1721
1722 /* SCIFA0 */
1723 GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
1724 GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
1725
1726 /* SCIFA1 */
1727 GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
1728 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
1729
1730 /* SCIFA2 */
1731 GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
1732 GPIO_FN(SCIFA2_SCK_PORT199),
1733 GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
1734 GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
1735
1736 /* SCIFA3 */
1737 GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
1738 GPIO_FN(SCIFA3_SCK_PORT116),
1739 GPIO_FN(SCIFA3_CTS_PORT117),
1740 GPIO_FN(SCIFA3_RXD_PORT174),
1741 GPIO_FN(SCIFA3_TXD_PORT175),
1742
1743 GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
1744 GPIO_FN(SCIFA3_SCK_PORT158),
1745 GPIO_FN(SCIFA3_CTS_PORT162),
1746 GPIO_FN(SCIFA3_RXD_PORT159),
1747 GPIO_FN(SCIFA3_TXD_PORT160),
1748
1749 /* SCIFA4 */
1750 GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
1751 GPIO_FN(SCIFA4_TXD_PORT13),
1752
1753 GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
1754 GPIO_FN(SCIFA4_TXD_PORT203),
1755
1756 GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
1757 GPIO_FN(SCIFA4_TXD_PORT93),
1758
1759 GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
1760 GPIO_FN(SCIFA4_SCK_PORT205),
1761
1762 /* SCIFA5 */
1763 GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
1764 GPIO_FN(SCIFA5_RXD_PORT10),
1765
1766 GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
1767 GPIO_FN(SCIFA5_TXD_PORT208),
1768
1769 GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
1770 GPIO_FN(SCIFA5_RXD_PORT92),
1771
1772 GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
1773 GPIO_FN(SCIFA5_SCK_PORT206),
1774
1775 /* SCIFA6 */
1776 GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
1777
1778 /* SCIFA7 */
1779 GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
1780
1781 /* SCIFAB */
1782 GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
1783 GPIO_FN(SCIFB_RXD_PORT191),
1784 GPIO_FN(SCIFB_TXD_PORT192),
1785 GPIO_FN(SCIFB_RTS_PORT186),
1786 GPIO_FN(SCIFB_CTS_PORT187),
1787
1788 GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
1789 GPIO_FN(SCIFB_RXD_PORT3),
1790 GPIO_FN(SCIFB_TXD_PORT4),
1791 GPIO_FN(SCIFB_RTS_PORT172),
1792 GPIO_FN(SCIFB_CTS_PORT173),
1793
1794 /* LCD0 */
1795 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1796 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1797 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1798 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1799 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1800 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1801 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1802 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1803 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1804 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1805 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1806
1807 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1808 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1809 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1810 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1811
1812 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1813 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1814 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1815 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1816
1817 /* LCD1 */
1818 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1819 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1820 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1821 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1822 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1823 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1824 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1825 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1826 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1827 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1828 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1829 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1830
1831 /* RSPI */
1832 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1833 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
1834 GPIO_FN(RSPI_MISO_A),
1835
1836 /* VIO CKO */
1837 GPIO_FN(VIO_CKO1),
1838 GPIO_FN(VIO_CKO2),
1839 GPIO_FN(VIO_CKO_1),
1840 GPIO_FN(VIO_CKO),
1841
1842 /* VIO0 */
1843 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
1844 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
1845 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
1846 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
1847 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
1848 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
1849
1850 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
1851 GPIO_FN(VIO0_D14_PORT25),
1852 GPIO_FN(VIO0_D15_PORT24),
1853
1854 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
1855 GPIO_FN(VIO0_D14_PORT95),
1856 GPIO_FN(VIO0_D15_PORT96),
1857
1858 /* VIO1 */
1859 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
1860 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
1861 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
1862 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
1863
1864 /* TPU0 */
1865 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
1866 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
1867 GPIO_FN(TPU0TO2_PORT202),
1868
1869 /* SSP1 0 */
1870 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
1871 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
1872 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
1873 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
1874
1875 /* SSP1 1 */
1876 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
1877 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
1878 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
1879
1880 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
1881 GPIO_FN(STP1_IPEN_PORT187),
1882
1883 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
1884 GPIO_FN(STP1_IPEN_PORT193),
1885
1886 /* SIM */
1887 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
1888 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1889 GPIO_FN(SIM_D_PORT199),
1890
1891 /* SDHI0 */
1892 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1893 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1894 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1895
1896 /* SDHI1 */
1897 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1898 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1899 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1900
1901 /* SDHI2 */
1902 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1903 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1904
1905 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1906 GPIO_FN(SDHI2_WP_PORT25),
1907
1908 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1909 GPIO_FN(SDHI2_CD_PORT202),
1910
1911 /* MSIOF2 */
1912 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1913 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
1914 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
1915 GPIO_FN(MSIOF2_RSCK),
1916
1917 /* KEYSC */
1918 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
1919 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
1920 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
1921 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
1922 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
1923
1924 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
1925 GPIO_FN(KEYIN1_PORT44),
1926 GPIO_FN(KEYIN2_PORT45),
1927 GPIO_FN(KEYIN3_PORT46),
1928
1929 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
1930 GPIO_FN(KEYIN1_PORT57),
1931 GPIO_FN(KEYIN2_PORT56),
1932 GPIO_FN(KEYIN3_PORT55),
1933
1934 /* VOU */
1935 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
1936 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
1937 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
1938 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
1939 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
1940 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
1941 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
1942
1943 /* MEMC */
1944 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
1945 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
1946 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
1947 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
1948 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
1949 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
1950 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
1951 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
1952 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1953 GPIO_FN(MEMC_A0),
1954
1955 /* MMC */
1956 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1957 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1958 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1959 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1960 GPIO_FN(MMC0_CLK_PORT66),
1961 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1962
1963 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1964 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1965 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1966 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1967 GPIO_FN(MMC1_CLK_PORT103),
1968 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1969
1970 /* MSIOF0 */
1971 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1972 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
1973 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
1974 GPIO_FN(MSIOF0_TSYNC),
1975
1976 /* MSIOF1 */
1977 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
1978 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1979
1980 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
1981 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
1982 GPIO_FN(MSIOF1_TSYNC_PORT120),
1983 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
1984
1985 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
1986 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
1987 GPIO_FN(MSIOF1_RXD_PORT75),
1988 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
1989
1990 /* GPIO */
1991 GPIO_FN(GPO0), GPIO_FN(GPI0),
1992 GPIO_FN(GPO1), GPIO_FN(GPI1),
1993
1994 /* USB0 */
1995 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
1996
1997 /* USB1 */
1998 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
1999
2000 /* BBIF1 */
2001 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
2002 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
2003 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
2004
2005 /* BBIF2 */
2006 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
2007 GPIO_FN(BBIF2_RXD2_PORT60),
2008 GPIO_FN(BBIF2_TSYNC2_PORT6),
2009 GPIO_FN(BBIF2_TSCK2_PORT59),
2010
2011 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
2012 GPIO_FN(BBIF2_TXD2_PORT183),
2013 GPIO_FN(BBIF2_TSCK2_PORT89),
2014 GPIO_FN(BBIF2_TSYNC2_PORT184),
2015
2016 /* BSC / FLCTL / PCMCIA */
2017 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
2018 GPIO_FN(CS5B), GPIO_FN(CS6A),
2019 GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
2020 GPIO_FN(CS5A_PORT19),
2021 GPIO_FN(IOIS16), /* ? */
2022
2023 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
2024 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
2025 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
2026 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
2027 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
2028 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
2029 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
2030 GPIO_FN(A26),
2031
2032 GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
2033 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
2034 GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
2035 GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
2036 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
2037 GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
2038 GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
2039 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
2040 GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
2041 GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
2042 GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
2043 GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
2044
2045 GPIO_FN(WE0_FWE), /* share with FLCTL */
2046 GPIO_FN(WE1),
2047 GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
2048 GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
2049 GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
2050 GPIO_FN(RD_FSC), /* share with FLCTL */
2051 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
2052 GPIO_FN(WAIT_PORT90),
2053
2054 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
2055
2056 /* IRDA */
2057 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
2058
2059 /* ATAPI */
2060 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
2061 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
2062 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
2063 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
2064 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
2065 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
2066 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
2067 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
2068 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
2069 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
2070
2071 /* RMII */
2072 GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
2073 GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
2074 GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
2075 GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
2076
2077 /* GEther */
2078 GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
2079 GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
2080 GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
2081 GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
2082 GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
2083 GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
2084 GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
2085 GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
2086 GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
2087 GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
2088 GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
2089 GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
2090
2091 /* DMA0 */
2092 GPIO_FN(DREQ0), GPIO_FN(DACK0),
2093
2094 /* DMA1 */
2095 GPIO_FN(DREQ1), GPIO_FN(DACK1),
2096
2097 /* SYSC */
2098 GPIO_FN(RESETOUTS),
2099
2100 /* IRREM */
2101 GPIO_FN(IROUT),
2102
2103 /* LCDC */
2104 GPIO_FN(LCDC0_SELECT),
2105 GPIO_FN(LCDC1_SELECT),
2106
2107 /* SDENC */
2108 GPIO_FN(SDENC_CPG),
2109 GPIO_FN(SDENC_DV_CLKI),
2110
2111 /* SYSC */
2112 GPIO_FN(RESETP_PULLUP),
2113 GPIO_FN(RESETP_PLAIN),
2114
2115 /* DEBUG */
2116 GPIO_FN(EDEBGREQ_PULLDOWN),
2117 GPIO_FN(EDEBGREQ_PULLUP),
2118
2119 GPIO_FN(TRACEAUD_FROM_VIO),
2120 GPIO_FN(TRACEAUD_FROM_LCDC0),
2121 GPIO_FN(TRACEAUD_FROM_MEMC),
2122};
2123
2124static struct pinmux_cfg_reg pinmux_config_regs[] = {
2125 PORTCR(0, 0xe6050000), /* PORT0CR */
2126 PORTCR(1, 0xe6050001), /* PORT1CR */
2127 PORTCR(2, 0xe6050002), /* PORT2CR */
2128 PORTCR(3, 0xe6050003), /* PORT3CR */
2129 PORTCR(4, 0xe6050004), /* PORT4CR */
2130 PORTCR(5, 0xe6050005), /* PORT5CR */
2131 PORTCR(6, 0xe6050006), /* PORT6CR */
2132 PORTCR(7, 0xe6050007), /* PORT7CR */
2133 PORTCR(8, 0xe6050008), /* PORT8CR */
2134 PORTCR(9, 0xe6050009), /* PORT9CR */
2135 PORTCR(10, 0xe605000a), /* PORT10CR */
2136 PORTCR(11, 0xe605000b), /* PORT11CR */
2137 PORTCR(12, 0xe605000c), /* PORT12CR */
2138 PORTCR(13, 0xe605000d), /* PORT13CR */
2139 PORTCR(14, 0xe605000e), /* PORT14CR */
2140 PORTCR(15, 0xe605000f), /* PORT15CR */
2141 PORTCR(16, 0xe6050010), /* PORT16CR */
2142 PORTCR(17, 0xe6050011), /* PORT17CR */
2143 PORTCR(18, 0xe6050012), /* PORT18CR */
2144 PORTCR(19, 0xe6050013), /* PORT19CR */
2145 PORTCR(20, 0xe6050014), /* PORT20CR */
2146 PORTCR(21, 0xe6050015), /* PORT21CR */
2147 PORTCR(22, 0xe6050016), /* PORT22CR */
2148 PORTCR(23, 0xe6050017), /* PORT23CR */
2149 PORTCR(24, 0xe6050018), /* PORT24CR */
2150 PORTCR(25, 0xe6050019), /* PORT25CR */
2151 PORTCR(26, 0xe605001a), /* PORT26CR */
2152 PORTCR(27, 0xe605001b), /* PORT27CR */
2153 PORTCR(28, 0xe605001c), /* PORT28CR */
2154 PORTCR(29, 0xe605001d), /* PORT29CR */
2155 PORTCR(30, 0xe605001e), /* PORT30CR */
2156 PORTCR(31, 0xe605001f), /* PORT31CR */
2157 PORTCR(32, 0xe6050020), /* PORT32CR */
2158 PORTCR(33, 0xe6050021), /* PORT33CR */
2159 PORTCR(34, 0xe6050022), /* PORT34CR */
2160 PORTCR(35, 0xe6050023), /* PORT35CR */
2161 PORTCR(36, 0xe6050024), /* PORT36CR */
2162 PORTCR(37, 0xe6050025), /* PORT37CR */
2163 PORTCR(38, 0xe6050026), /* PORT38CR */
2164 PORTCR(39, 0xe6050027), /* PORT39CR */
2165 PORTCR(40, 0xe6050028), /* PORT40CR */
2166 PORTCR(41, 0xe6050029), /* PORT41CR */
2167 PORTCR(42, 0xe605002a), /* PORT42CR */
2168 PORTCR(43, 0xe605002b), /* PORT43CR */
2169 PORTCR(44, 0xe605002c), /* PORT44CR */
2170 PORTCR(45, 0xe605002d), /* PORT45CR */
2171 PORTCR(46, 0xe605002e), /* PORT46CR */
2172 PORTCR(47, 0xe605002f), /* PORT47CR */
2173 PORTCR(48, 0xe6050030), /* PORT48CR */
2174 PORTCR(49, 0xe6050031), /* PORT49CR */
2175 PORTCR(50, 0xe6050032), /* PORT50CR */
2176 PORTCR(51, 0xe6050033), /* PORT51CR */
2177 PORTCR(52, 0xe6050034), /* PORT52CR */
2178 PORTCR(53, 0xe6050035), /* PORT53CR */
2179 PORTCR(54, 0xe6050036), /* PORT54CR */
2180 PORTCR(55, 0xe6050037), /* PORT55CR */
2181 PORTCR(56, 0xe6050038), /* PORT56CR */
2182 PORTCR(57, 0xe6050039), /* PORT57CR */
2183 PORTCR(58, 0xe605003a), /* PORT58CR */
2184 PORTCR(59, 0xe605003b), /* PORT59CR */
2185 PORTCR(60, 0xe605003c), /* PORT60CR */
2186 PORTCR(61, 0xe605003d), /* PORT61CR */
2187 PORTCR(62, 0xe605003e), /* PORT62CR */
2188 PORTCR(63, 0xe605003f), /* PORT63CR */
2189 PORTCR(64, 0xe6050040), /* PORT64CR */
2190 PORTCR(65, 0xe6050041), /* PORT65CR */
2191 PORTCR(66, 0xe6050042), /* PORT66CR */
2192 PORTCR(67, 0xe6050043), /* PORT67CR */
2193 PORTCR(68, 0xe6050044), /* PORT68CR */
2194 PORTCR(69, 0xe6050045), /* PORT69CR */
2195 PORTCR(70, 0xe6050046), /* PORT70CR */
2196 PORTCR(71, 0xe6050047), /* PORT71CR */
2197 PORTCR(72, 0xe6050048), /* PORT72CR */
2198 PORTCR(73, 0xe6050049), /* PORT73CR */
2199 PORTCR(74, 0xe605004a), /* PORT74CR */
2200 PORTCR(75, 0xe605004b), /* PORT75CR */
2201 PORTCR(76, 0xe605004c), /* PORT76CR */
2202 PORTCR(77, 0xe605004d), /* PORT77CR */
2203 PORTCR(78, 0xe605004e), /* PORT78CR */
2204 PORTCR(79, 0xe605004f), /* PORT79CR */
2205 PORTCR(80, 0xe6050050), /* PORT80CR */
2206 PORTCR(81, 0xe6050051), /* PORT81CR */
2207 PORTCR(82, 0xe6050052), /* PORT82CR */
2208 PORTCR(83, 0xe6050053), /* PORT83CR */
2209
2210 PORTCR(84, 0xe6051054), /* PORT84CR */
2211 PORTCR(85, 0xe6051055), /* PORT85CR */
2212 PORTCR(86, 0xe6051056), /* PORT86CR */
2213 PORTCR(87, 0xe6051057), /* PORT87CR */
2214 PORTCR(88, 0xe6051058), /* PORT88CR */
2215 PORTCR(89, 0xe6051059), /* PORT89CR */
2216 PORTCR(90, 0xe605105a), /* PORT90CR */
2217 PORTCR(91, 0xe605105b), /* PORT91CR */
2218 PORTCR(92, 0xe605105c), /* PORT92CR */
2219 PORTCR(93, 0xe605105d), /* PORT93CR */
2220 PORTCR(94, 0xe605105e), /* PORT94CR */
2221 PORTCR(95, 0xe605105f), /* PORT95CR */
2222 PORTCR(96, 0xe6051060), /* PORT96CR */
2223 PORTCR(97, 0xe6051061), /* PORT97CR */
2224 PORTCR(98, 0xe6051062), /* PORT98CR */
2225 PORTCR(99, 0xe6051063), /* PORT99CR */
2226 PORTCR(100, 0xe6051064), /* PORT100CR */
2227 PORTCR(101, 0xe6051065), /* PORT101CR */
2228 PORTCR(102, 0xe6051066), /* PORT102CR */
2229 PORTCR(103, 0xe6051067), /* PORT103CR */
2230 PORTCR(104, 0xe6051068), /* PORT104CR */
2231 PORTCR(105, 0xe6051069), /* PORT105CR */
2232 PORTCR(106, 0xe605106a), /* PORT106CR */
2233 PORTCR(107, 0xe605106b), /* PORT107CR */
2234 PORTCR(108, 0xe605106c), /* PORT108CR */
2235 PORTCR(109, 0xe605106d), /* PORT109CR */
2236 PORTCR(110, 0xe605106e), /* PORT110CR */
2237 PORTCR(111, 0xe605106f), /* PORT111CR */
2238 PORTCR(112, 0xe6051070), /* PORT112CR */
2239 PORTCR(113, 0xe6051071), /* PORT113CR */
2240 PORTCR(114, 0xe6051072), /* PORT114CR */
2241
2242 PORTCR(115, 0xe6052073), /* PORT115CR */
2243 PORTCR(116, 0xe6052074), /* PORT116CR */
2244 PORTCR(117, 0xe6052075), /* PORT117CR */
2245 PORTCR(118, 0xe6052076), /* PORT118CR */
2246 PORTCR(119, 0xe6052077), /* PORT119CR */
2247 PORTCR(120, 0xe6052078), /* PORT120CR */
2248 PORTCR(121, 0xe6052079), /* PORT121CR */
2249 PORTCR(122, 0xe605207a), /* PORT122CR */
2250 PORTCR(123, 0xe605207b), /* PORT123CR */
2251 PORTCR(124, 0xe605207c), /* PORT124CR */
2252 PORTCR(125, 0xe605207d), /* PORT125CR */
2253 PORTCR(126, 0xe605207e), /* PORT126CR */
2254 PORTCR(127, 0xe605207f), /* PORT127CR */
2255 PORTCR(128, 0xe6052080), /* PORT128CR */
2256 PORTCR(129, 0xe6052081), /* PORT129CR */
2257 PORTCR(130, 0xe6052082), /* PORT130CR */
2258 PORTCR(131, 0xe6052083), /* PORT131CR */
2259 PORTCR(132, 0xe6052084), /* PORT132CR */
2260 PORTCR(133, 0xe6052085), /* PORT133CR */
2261 PORTCR(134, 0xe6052086), /* PORT134CR */
2262 PORTCR(135, 0xe6052087), /* PORT135CR */
2263 PORTCR(136, 0xe6052088), /* PORT136CR */
2264 PORTCR(137, 0xe6052089), /* PORT137CR */
2265 PORTCR(138, 0xe605208a), /* PORT138CR */
2266 PORTCR(139, 0xe605208b), /* PORT139CR */
2267 PORTCR(140, 0xe605208c), /* PORT140CR */
2268 PORTCR(141, 0xe605208d), /* PORT141CR */
2269 PORTCR(142, 0xe605208e), /* PORT142CR */
2270 PORTCR(143, 0xe605208f), /* PORT143CR */
2271 PORTCR(144, 0xe6052090), /* PORT144CR */
2272 PORTCR(145, 0xe6052091), /* PORT145CR */
2273 PORTCR(146, 0xe6052092), /* PORT146CR */
2274 PORTCR(147, 0xe6052093), /* PORT147CR */
2275 PORTCR(148, 0xe6052094), /* PORT148CR */
2276 PORTCR(149, 0xe6052095), /* PORT149CR */
2277 PORTCR(150, 0xe6052096), /* PORT150CR */
2278 PORTCR(151, 0xe6052097), /* PORT151CR */
2279 PORTCR(152, 0xe6052098), /* PORT152CR */
2280 PORTCR(153, 0xe6052099), /* PORT153CR */
2281 PORTCR(154, 0xe605209a), /* PORT154CR */
2282 PORTCR(155, 0xe605209b), /* PORT155CR */
2283 PORTCR(156, 0xe605209c), /* PORT156CR */
2284 PORTCR(157, 0xe605209d), /* PORT157CR */
2285 PORTCR(158, 0xe605209e), /* PORT158CR */
2286 PORTCR(159, 0xe605209f), /* PORT159CR */
2287 PORTCR(160, 0xe60520a0), /* PORT160CR */
2288 PORTCR(161, 0xe60520a1), /* PORT161CR */
2289 PORTCR(162, 0xe60520a2), /* PORT162CR */
2290 PORTCR(163, 0xe60520a3), /* PORT163CR */
2291 PORTCR(164, 0xe60520a4), /* PORT164CR */
2292 PORTCR(165, 0xe60520a5), /* PORT165CR */
2293 PORTCR(166, 0xe60520a6), /* PORT166CR */
2294 PORTCR(167, 0xe60520a7), /* PORT167CR */
2295 PORTCR(168, 0xe60520a8), /* PORT168CR */
2296 PORTCR(169, 0xe60520a9), /* PORT169CR */
2297 PORTCR(170, 0xe60520aa), /* PORT170CR */
2298 PORTCR(171, 0xe60520ab), /* PORT171CR */
2299 PORTCR(172, 0xe60520ac), /* PORT172CR */
2300 PORTCR(173, 0xe60520ad), /* PORT173CR */
2301 PORTCR(174, 0xe60520ae), /* PORT174CR */
2302 PORTCR(175, 0xe60520af), /* PORT175CR */
2303 PORTCR(176, 0xe60520b0), /* PORT176CR */
2304 PORTCR(177, 0xe60520b1), /* PORT177CR */
2305 PORTCR(178, 0xe60520b2), /* PORT178CR */
2306 PORTCR(179, 0xe60520b3), /* PORT179CR */
2307 PORTCR(180, 0xe60520b4), /* PORT180CR */
2308 PORTCR(181, 0xe60520b5), /* PORT181CR */
2309 PORTCR(182, 0xe60520b6), /* PORT182CR */
2310 PORTCR(183, 0xe60520b7), /* PORT183CR */
2311 PORTCR(184, 0xe60520b8), /* PORT184CR */
2312 PORTCR(185, 0xe60520b9), /* PORT185CR */
2313 PORTCR(186, 0xe60520ba), /* PORT186CR */
2314 PORTCR(187, 0xe60520bb), /* PORT187CR */
2315 PORTCR(188, 0xe60520bc), /* PORT188CR */
2316 PORTCR(189, 0xe60520bd), /* PORT189CR */
2317 PORTCR(190, 0xe60520be), /* PORT190CR */
2318 PORTCR(191, 0xe60520bf), /* PORT191CR */
2319 PORTCR(192, 0xe60520c0), /* PORT192CR */
2320 PORTCR(193, 0xe60520c1), /* PORT193CR */
2321 PORTCR(194, 0xe60520c2), /* PORT194CR */
2322 PORTCR(195, 0xe60520c3), /* PORT195CR */
2323 PORTCR(196, 0xe60520c4), /* PORT196CR */
2324 PORTCR(197, 0xe60520c5), /* PORT197CR */
2325 PORTCR(198, 0xe60520c6), /* PORT198CR */
2326 PORTCR(199, 0xe60520c7), /* PORT199CR */
2327 PORTCR(200, 0xe60520c8), /* PORT200CR */
2328 PORTCR(201, 0xe60520c9), /* PORT201CR */
2329 PORTCR(202, 0xe60520ca), /* PORT202CR */
2330 PORTCR(203, 0xe60520cb), /* PORT203CR */
2331 PORTCR(204, 0xe60520cc), /* PORT204CR */
2332 PORTCR(205, 0xe60520cd), /* PORT205CR */
2333 PORTCR(206, 0xe60520ce), /* PORT206CR */
2334 PORTCR(207, 0xe60520cf), /* PORT207CR */
2335 PORTCR(208, 0xe60520d0), /* PORT208CR */
2336 PORTCR(209, 0xe60520d1), /* PORT209CR */
2337
2338 PORTCR(210, 0xe60530d2), /* PORT210CR */
2339 PORTCR(211, 0xe60530d3), /* PORT211CR */
2340
2341 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2342 MSEL1CR_31_0, MSEL1CR_31_1,
2343 MSEL1CR_30_0, MSEL1CR_30_1,
2344 MSEL1CR_29_0, MSEL1CR_29_1,
2345 MSEL1CR_28_0, MSEL1CR_28_1,
2346 MSEL1CR_27_0, MSEL1CR_27_1,
2347 MSEL1CR_26_0, MSEL1CR_26_1,
2348 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2349 0, 0, 0, 0, 0, 0, 0, 0,
2350 MSEL1CR_16_0, MSEL1CR_16_1,
2351 MSEL1CR_15_0, MSEL1CR_15_1,
2352 MSEL1CR_14_0, MSEL1CR_14_1,
2353 MSEL1CR_13_0, MSEL1CR_13_1,
2354 MSEL1CR_12_0, MSEL1CR_12_1,
2355 0, 0, 0, 0,
2356 MSEL1CR_9_0, MSEL1CR_9_1,
2357 0, 0,
2358 MSEL1CR_7_0, MSEL1CR_7_1,
2359 MSEL1CR_6_0, MSEL1CR_6_1,
2360 MSEL1CR_5_0, MSEL1CR_5_1,
2361 MSEL1CR_4_0, MSEL1CR_4_1,
2362 MSEL1CR_3_0, MSEL1CR_3_1,
2363 MSEL1CR_2_0, MSEL1CR_2_1,
2364 0, 0,
2365 MSEL1CR_0_0, MSEL1CR_0_1,
2366 }
2367 },
2368 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2369 0, 0, 0, 0, 0, 0, 0, 0,
2370 0, 0, 0, 0, 0, 0, 0, 0,
2371 0, 0, 0, 0, 0, 0, 0, 0,
2372 0, 0, 0, 0, 0, 0, 0, 0,
2373 MSEL3CR_15_0, MSEL3CR_15_1,
2374 0, 0, 0, 0, 0, 0, 0, 0,
2375 0, 0, 0, 0, 0, 0, 0, 0,
2376 MSEL3CR_6_0, MSEL3CR_6_1,
2377 0, 0, 0, 0, 0, 0, 0, 0,
2378 0, 0, 0, 0,
2379 }
2380 },
2381 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2382 0, 0, 0, 0, 0, 0, 0, 0,
2383 0, 0, 0, 0, 0, 0, 0, 0,
2384 0, 0, 0, 0, 0, 0, 0, 0,
2385 MSEL4CR_19_0, MSEL4CR_19_1,
2386 MSEL4CR_18_0, MSEL4CR_18_1,
2387 0, 0, 0, 0,
2388 MSEL4CR_15_0, MSEL4CR_15_1,
2389 0, 0, 0, 0, 0, 0, 0, 0,
2390 MSEL4CR_10_0, MSEL4CR_10_1,
2391 0, 0, 0, 0, 0, 0,
2392 MSEL4CR_6_0, MSEL4CR_6_1,
2393 0, 0,
2394 MSEL4CR_4_0, MSEL4CR_4_1,
2395 0, 0, 0, 0,
2396 MSEL4CR_1_0, MSEL4CR_1_1,
2397 0, 0,
2398 }
2399 },
2400 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
2401 MSEL5CR_31_0, MSEL5CR_31_1,
2402 MSEL5CR_30_0, MSEL5CR_30_1,
2403 MSEL5CR_29_0, MSEL5CR_29_1,
2404 0, 0,
2405 MSEL5CR_27_0, MSEL5CR_27_1,
2406 0, 0,
2407 MSEL5CR_25_0, MSEL5CR_25_1,
2408 0, 0,
2409 MSEL5CR_23_0, MSEL5CR_23_1,
2410 0, 0,
2411 MSEL5CR_21_0, MSEL5CR_21_1,
2412 0, 0,
2413 MSEL5CR_19_0, MSEL5CR_19_1,
2414 0, 0,
2415 MSEL5CR_17_0, MSEL5CR_17_1,
2416 0, 0,
2417 MSEL5CR_15_0, MSEL5CR_15_1,
2418 MSEL5CR_14_0, MSEL5CR_14_1,
2419 MSEL5CR_13_0, MSEL5CR_13_1,
2420 MSEL5CR_12_0, MSEL5CR_12_1,
2421 MSEL5CR_11_0, MSEL5CR_11_1,
2422 MSEL5CR_10_0, MSEL5CR_10_1,
2423 0, 0,
2424 MSEL5CR_8_0, MSEL5CR_8_1,
2425 MSEL5CR_7_0, MSEL5CR_7_1,
2426 MSEL5CR_6_0, MSEL5CR_6_1,
2427 MSEL5CR_5_0, MSEL5CR_5_1,
2428 MSEL5CR_4_0, MSEL5CR_4_1,
2429 MSEL5CR_3_0, MSEL5CR_3_1,
2430 MSEL5CR_2_0, MSEL5CR_2_1,
2431 0, 0,
2432 MSEL5CR_0_0, MSEL5CR_0_1,
2433 }
2434 },
2435 { },
2436};
2437
2438static struct pinmux_data_reg pinmux_data_regs[] = {
2439 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2440 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2441 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2442 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2443 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2444 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2445 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2446 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2447 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
2448 },
2449 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
2450 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2451 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2452 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2453 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2454 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
2455 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2456 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2457 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
2458 },
2459 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
2460 0, 0, 0, 0,
2461 0, 0, 0, 0,
2462 0, 0, 0, 0,
2463 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2464 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2465 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2466 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2467 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
2468 },
2469 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
2470 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2471 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2472 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2473 0, 0, 0, 0,
2474 0, 0, 0, 0,
2475 0, 0, 0, 0,
2476 0, 0, 0, 0,
2477 0, 0, 0, 0 }
2478 },
2479 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
2480 0, 0, 0, 0,
2481 0, 0, 0, 0,
2482 0, 0, 0, 0,
2483 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2484 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2485 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2486 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2487 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
2488 },
2489 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
2490 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2491 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2492 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2493 PORT115_DATA, 0, 0, 0,
2494 0, 0, 0, 0,
2495 0, 0, 0, 0,
2496 0, 0, 0, 0,
2497 0, 0, 0, 0 }
2498 },
2499 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
2500 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2501 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2502 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2503 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2504 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2505 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2506 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2507 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
2508 },
2509 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
2510 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2511 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2512 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2513 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2514 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2515 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2516 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2517 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
2518 },
2519 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
2520 0, 0, 0, 0,
2521 0, 0, 0, 0,
2522 0, 0, 0, 0,
2523 0, 0, PORT209_DATA, PORT208_DATA,
2524 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2525 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2526 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2527 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
2528 },
2529 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
2530 0, 0, 0, 0,
2531 0, 0, 0, 0,
2532 0, 0, 0, 0,
2533 PORT211_DATA, PORT210_DATA, 0, 0,
2534 0, 0, 0, 0,
2535 0, 0, 0, 0,
2536 0, 0, 0, 0,
2537 0, 0, 0, 0 }
2538 },
2539 { },
2540};
2541
2542static struct pinmux_irq pinmux_irqs[] = {
2543 PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */
2544 PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */
2545 PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */
2546 PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */
2547 PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */
2548 PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */
2549 PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */
2550 PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */
2551 PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */
2552 PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */
2553 PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */
2554 PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */
2555 PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */
2556 PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */
2557 PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */
2558 PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */
2559 PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */
2560 PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */
2561 PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */
2562 PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */
2563 PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */
2564 PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */
2565 PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */
2566 PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */
2567 PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */
2568 PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */
2569 PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */
2570 PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */
2571 PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */
2572 PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */
2573 PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */
2574 PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */
2575};
2576
2577static struct pinmux_info r8a7740_pinmux_info = {
2578 .name = "r8a7740_pfc",
2579 .reserved_id = PINMUX_RESERVED,
2580 .data = { PINMUX_DATA_BEGIN,
2581 PINMUX_DATA_END },
2582 .input = { PINMUX_INPUT_BEGIN,
2583 PINMUX_INPUT_END },
2584 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
2585 PINMUX_INPUT_PULLUP_END },
2586 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
2587 PINMUX_INPUT_PULLDOWN_END },
2588 .output = { PINMUX_OUTPUT_BEGIN,
2589 PINMUX_OUTPUT_END },
2590 .mark = { PINMUX_MARK_BEGIN,
2591 PINMUX_MARK_END },
2592 .function = { PINMUX_FUNCTION_BEGIN,
2593 PINMUX_FUNCTION_END },
2594
2595 .first_gpio = GPIO_PORT0,
2596 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
2597
2598 .gpios = pinmux_gpios,
2599 .cfg_regs = pinmux_config_regs,
2600 .data_regs = pinmux_data_regs,
2601
2602 .gpio_data = pinmux_data,
2603 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2604
2605 .gpio_irq = pinmux_irqs,
2606 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2607};
2608
2609void r8a7740_pinmux_init(void)
2610{
2611 register_pinmux(&r8a7740_pinmux_info);
2612}