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Simon Glass4a56f102015-01-27 22:13:47 -07001/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <mmc.h>
9#include <pci_ids.h>
Bin Meng947391c2015-07-30 03:49:18 -070010#include <asm/irq.h>
Bin Mengdc597802015-10-11 21:37:43 -070011#include <asm/mrccache.h>
Simon Glass4a56f102015-01-27 22:13:47 -070012#include <asm/post.h>
13
14static struct pci_device_id mmc_supported[] = {
15 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
16 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
Simon Glass0b619282015-11-29 13:18:08 -070017 {},
Simon Glass4a56f102015-01-27 22:13:47 -070018};
19
20int cpu_mmc_init(bd_t *bis)
21{
Simon Glass0b619282015-11-29 13:18:08 -070022 return pci_mmc_init("ValleyView SDHCI", mmc_supported);
Simon Glass4a56f102015-01-27 22:13:47 -070023}
24
Simon Glassa815df72015-08-04 12:34:02 -060025#ifndef CONFIG_EFI_APP
Simon Glass4a56f102015-01-27 22:13:47 -070026int arch_cpu_init(void)
27{
28 int ret;
29
30 post_code(POST_CPU_INIT);
Simon Glass4a56f102015-01-27 22:13:47 -070031
32 ret = x86_cpu_init_f();
33 if (ret)
34 return ret;
35
36 return 0;
37}
Bin Meng947391c2015-07-30 03:49:18 -070038
39int arch_misc_init(void)
40{
Simon Glass5cc82b82015-08-10 07:05:12 -060041 if (!ll_boot_init())
42 return 0;
Simon Glass888697a2015-08-10 07:05:10 -060043
Bin Mengdc597802015-10-11 21:37:43 -070044#ifdef CONFIG_ENABLE_MRC_CACHE
45 /*
46 * We intend not to check any return value here, as even MRC cache
47 * is not saved successfully, it is not a severe error that will
48 * prevent system from continuing to boot.
49 */
50 mrccache_save();
51#endif
52
Simon Glass754f55e2016-01-19 21:32:26 -070053 return 0;
Bin Meng947391c2015-07-30 03:49:18 -070054}
Bin Mengdc597802015-10-11 21:37:43 -070055
Simon Glassa815df72015-08-04 12:34:02 -060056#endif
Bin Meng71d7c2f2015-10-11 21:37:45 -070057
58void reset_cpu(ulong addr)
59{
60 /* cold reset */
61 x86_full_reset();
62}