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git01.mediatek.com / filogic / uboot / 3659be07dac35583e912f698790f5bcf1e92b999 / . / arch / arm / dts / imx6qdl-dhcom-som.dtsi
blob: 5d10c40313cbd220c09d771b7c9740baf47d01e2 [file] [log] [blame]
Marek Vasut00d51662021-12-31 00:58:08 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015-2021 DH electronics GmbH
4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5 */
6
7#include <dt-bindings/pwm/pwm.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/clock/imx6qdl-clock.h>
10#include <dt-bindings/input/input.h>
11
12/ {
13 aliases {
14 i2c0 = &i2c2;
15 i2c1 = &i2c1;
16 i2c2 = &i2c3;
17 mmc0 = &usdhc2;
18 mmc1 = &usdhc3;
19 mmc2 = &usdhc4;
20 mmc3 = &usdhc1;
21 rtc0 = &rtc_i2c;
22 rtc1 = &snvs_rtc;
23 serial0 = &uart1;
24 serial1 = &uart5;
25 serial2 = &uart4;
26 serial3 = &uart2;
27 serial4 = &uart3;
28 };
29
30 memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
31 device_type = "memory";
32 reg = <0x10000000 0x20000000>;
33 };
34
35 reg_3p3v: regulator-3P3V {
36 compatible = "regulator-fixed";
37 regulator-always-on;
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-name = "3P3V";
41 };
42
43 reg_eth_vio: regulator-eth-vio {
44 compatible = "regulator-fixed";
45 gpio = <&gpio1 7 0>;
46 pinctrl-0 = <&pinctrl_enet_vio>;
47 pinctrl-names = "default";
48 regulator-always-on;
49 regulator-boot-on;
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-name = "eth_vio";
53 vin-supply = <&sw2_reg>;
54 };
55
56 /* OE pin of the latch is low active */
57 reg_latch_oe_on: regulator-latch-oe-on {
58 compatible = "regulator-fixed";
59 gpio = <&gpio3 22 0>;
60 regulator-always-on;
61 regulator-name = "latch_oe_on";
62 };
63
64 reg_usb_h1_vbus: regulator-usb-h1-vbus {
65 compatible = "regulator-fixed";
66 enable-active-high;
67 gpio = <&gpio3 31 0>;
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 regulator-name = "usb_h1_vbus";
71 };
72
73 reg_usb_otg_vbus: regulator-usb-otg-vbus {
74 compatible = "regulator-fixed";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 regulator-name = "usb_otg_vbus";
78 };
79};
80
81&can1 {
82 pinctrl-0 = <&pinctrl_flexcan1>;
83 pinctrl-names = "default";
84 status = "okay";
85};
86
87/*
88 * Special SoM hardware required which uses the pins from micro SD card. The
89 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
90 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on
91 * the board device tree file, the micro SD card must be disabled and the uart1
92 * rts/cts must be disabled or output on other DHCOM pins.
93 */
94&can2 {
95 pinctrl-0 = <&pinctrl_flexcan2>;
96 pinctrl-names = "default";
97 status = "disabled";
98};
99
100&ecspi1 {
101 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
102 pinctrl-0 = <&pinctrl_ecspi1>;
103 pinctrl-names = "default";
104 status = "okay";
105
106 flash@0 { /* S25FL116K */
107 #address-cells = <1>;
108 #size-cells = <1>;
109 compatible = "jedec,spi-nor";
110 m25p,fast-read;
111 reg = <0>;
112 spi-max-frequency = <50000000>;
113 };
114};
115
116&ecspi2 {
117 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
118 pinctrl-0 = <&pinctrl_ecspi2>;
119 pinctrl-names = "default";
120 status = "disabled";
121};
122
123&fec {
124 phy-mode = "rmii";
125 phy-handle = <&ethphy0>;
126 pinctrl-0 = <&pinctrl_enet_100M>;
127 pinctrl-names = "default";
128 status = "okay";
129
130 mdio {
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
135 compatible = "ethernet-phy-ieee802.3-c22";
136 interrupt-parent = <&gpio4>;
137 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
138 pinctrl-0 = <&pinctrl_ethphy0>;
139 pinctrl-names = "default";
140 reg = <0>;
141 reset-assert-us = <1000>;
142 reset-deassert-us = <1000>;
143 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
144 smsc,disable-energy-detect; /* Make plugin detection reliable */
145 };
146 };
147};
148
149&gpio1 {
150 gpio-line-names =
151 "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
152 "", "", "", "", "", "", "", "",
153 "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
154 "", "", "", "", "", "", "", "";
155};
156
157&gpio2 {
158 gpio-line-names =
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
162 "", "", "", "", "", "", "", "";
163};
164
165&gpio3 {
166 gpio-line-names =
167 "", "", "", "", "", "", "", "",
168 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
170 "", "", "", "DHCOM-G", "", "", "", "";
171};
172
173&gpio4 {
174 gpio-line-names =
175 "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
176 "DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
177 "", "", "", "", "DHCOM-F", "", "", "",
178 "", "", "", "", "", "", "", "";
179};
180
181&gpio5 {
182 gpio-line-names =
183 "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "",
185 "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
186 "", "", "", "", "", "", "", "";
187};
188
189&gpio6 {
190 gpio-line-names =
191 "", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
192 "", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
193 "", "", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "";
195};
196
197&gpio7 {
198 gpio-line-names =
199 "DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
200 "", "", "", "", "", "DHCOM-P", "", "",
201 "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "";
203};
204
205&i2c1 {
206 /*
207 * Info: According to erratum ERR007805 clock frequency limit is 375000.
208 * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
209 * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
210 * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
211 */
212 clock-frequency = <100000>;
213 pinctrl-0 = <&pinctrl_i2c1>;
214 pinctrl-1 = <&pinctrl_i2c1_gpio>;
215 pinctrl-names = "default", "gpio";
216 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
217 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
218 status = "okay";
219};
220
221&i2c2 {
222 /* Info: Clock frequency limit is 375000 (for details see i2c1) */
223 clock-frequency = <100000>;
224 pinctrl-0 = <&pinctrl_i2c2>;
225 pinctrl-1 = <&pinctrl_i2c2_gpio>;
226 pinctrl-names = "default", "gpio";
227 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
228 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
229 status = "okay";
230};
231
232&i2c3 {
233 /* Info: Clock frequency limit is 375000 (for details see i2c1) */
234 clock-frequency = <100000>;
235 pinctrl-0 = <&pinctrl_i2c3>;
236 pinctrl-1 = <&pinctrl_i2c3_gpio>;
237 pinctrl-names = "default", "gpio";
238 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
239 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
240 status = "okay";
241
242 ltc3676: pmic@3c {
243 compatible = "lltc,ltc3676";
244 interrupt-parent = <&gpio5>;
245 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
246 pinctrl-0 = <&pinctrl_pmic>;
247 pinctrl-names = "default";
248 reg = <0x3c>;
249
250 regulators {
251 sw1_reg: sw1 {
252 lltc,fb-voltage-divider = <100000 110000>;
253 regulator-always-on;
254 regulator-boot-on;
255 regulator-max-microvolt = <1527272>;
256 regulator-min-microvolt = <787500>;
257 regulator-ramp-delay = <7000>;
258 regulator-suspend-mem-microvolt = <1040000>;
259 };
260
261 sw2_reg: sw2 {
262 lltc,fb-voltage-divider = <100000 28000>;
263 regulator-always-on;
264 regulator-boot-on;
265 regulator-max-microvolt = <3657142>;
266 regulator-min-microvolt = <1885714>;
267 regulator-ramp-delay = <7000>;
268 };
269
270 sw3_reg: sw3 {
271 lltc,fb-voltage-divider = <100000 110000>;
272 regulator-always-on;
273 regulator-boot-on;
274 regulator-max-microvolt = <1527272>;
275 regulator-min-microvolt = <787500>;
276 regulator-ramp-delay = <7000>;
277 regulator-suspend-mem-microvolt = <980000>;
278 };
279
280 sw4_reg: sw4 {
281 lltc,fb-voltage-divider = <100000 93100>;
282 regulator-always-on;
283 regulator-boot-on;
284 regulator-max-microvolt = <1659291>;
285 regulator-min-microvolt = <855571>;
286 regulator-ramp-delay = <7000>;
287 };
288
289 ldo1_reg: ldo1 {
290 lltc,fb-voltage-divider = <102000 29400>;
291 regulator-always-on;
292 regulator-boot-on;
293 regulator-max-microvolt = <3240306>;
294 regulator-min-microvolt = <3240306>;
295 };
296
297 ldo2_reg: ldo2 {
298 lltc,fb-voltage-divider = <100000 41200>;
299 regulator-always-on;
300 regulator-boot-on;
301 regulator-max-microvolt = <2484708>;
302 regulator-min-microvolt = <2484708>;
303 };
304 };
305 };
306
307 touchscreen@49 { /* TSC2004 */
308 compatible = "ti,tsc2004";
309 interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
310 pinctrl-0 = <&pinctrl_tsc2004>;
311 pinctrl-names = "default";
312 reg = <0x49>;
313 vio-supply = <&reg_3p3v>;
314 status = "disabled";
315 };
316
317 eeprom@50 {
318 compatible = "atmel,24c02";
319 pagesize = <16>;
320 reg = <0x50>;
321 };
322
323 rtc_i2c: rtc@56 {
324 compatible = "microcrystal,rv3029";
325 interrupt-parent = <&gpio7>;
326 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
327 pinctrl-0 = <&pinctrl_rtc>;
328 pinctrl-names = "default";
329 reg = <0x56>;
330 };
331};
332
333&pcie {
334 pinctrl-0 = <&pinctrl_pcie>;
335 pinctrl-names = "default";
336};
337
338&pwm1 {
339 pinctrl-0 = <&pinctrl_pwm1>;
340 pinctrl-names = "default";
341};
342
343&reg_arm {
344 vin-supply = <&sw3_reg>;
345};
346
347&reg_pu {
348 vin-supply = <&sw1_reg>;
349};
350
351&reg_soc {
352 vin-supply = <&sw1_reg>;
353};
354
355&reg_vdd1p1 {
356 vin-supply = <&sw2_reg>;
357};
358
359&reg_vdd2p5 {
360 vin-supply = <&sw2_reg>;
361};
362
363&uart1 { /* DHCOM UART1 */
364 dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
365 dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
366 dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
367 rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
368 pinctrl-0 = <&pinctrl_uart1>;
369 pinctrl-names = "default";
370 uart-has-rtscts;
371 status = "okay";
372};
373
374&uart4 { /* DHCOM UART3 */
375 pinctrl-0 = <&pinctrl_uart4>;
376 pinctrl-names = "default";
377 status = "okay";
378};
379
380&uart5 { /* DHCOM UART2 */
381 pinctrl-0 = <&pinctrl_uart5>;
382 pinctrl-names = "default";
383 uart-has-rtscts;
384 status = "okay";
385};
386
387&usbh1 {
388 dr_mode = "host";
389 pinctrl-0 = <&pinctrl_usbh1>;
390 pinctrl-names = "default";
391 vbus-supply = <&reg_usb_h1_vbus>;
392 status = "okay";
393};
394
395&usbotg {
396 disable-over-current;
397 dr_mode = "otg";
398 pinctrl-0 = <&pinctrl_usbotg>;
399 pinctrl-names = "default";
400 vbus-supply = <&reg_usb_otg_vbus>;
401 status = "okay";
402};
403
404&usdhc2 { /* External SD card via DHCOM */
405 cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
406 keep-power-in-suspend;
407 pinctrl-0 = <&pinctrl_usdhc2>;
408 pinctrl-names = "default";
409 status = "disabled";
410};
411
412&usdhc3 { /* Micro SD card on module */
413 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
414 fsl,wp-controller;
415 keep-power-in-suspend;
416 pinctrl-0 = <&pinctrl_usdhc3>;
417 pinctrl-names = "default";
418 status = "okay";
419};
420
421&usdhc4 { /* eMMC on module */
422 bus-width = <8>;
423 keep-power-in-suspend;
424 no-1-8-v;
425 non-removable;
426 pinctrl-0 = <&pinctrl_usdhc4>;
427 pinctrl-names = "default";
428 status = "okay";
429};
430
431&weim {
432 #address-cells = <2>;
433 #size-cells = <1>;
434 fsl,weim-cs-gpr = <&gpr>;
435 pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
436 pinctrl-names = "default";
437 /* It is necessary to setup 2x 64MB otherwise setting gpr fails */
438 ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
439 <1 0 0x0c000000 0x04000000>; /* CS1 */
440 status = "disabled";
441};
442
443&iomuxc {
444 pinctrl-0 = <
445 &pinctrl_hog_base
446 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
447 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
448 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
449 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
450 &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
451 &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
452 &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
453 &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
454 >;
455 pinctrl-names = "default";
456
457 pinctrl_hog_base: hog-base-grp {
458 fsl,pins = <
459 /* GPIOs for memory coding */
460 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
461 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
462 /* GPIOs for hardware coding */
463 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
464 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
465 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
466 >;
467 };
468
469 /* DHCOM GPIOs */
470 pinctrl_dhcom_a: dhcom-a-grp {
471 fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>;
472 };
473
474 pinctrl_dhcom_b: dhcom-b-grp {
475 fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>;
476 };
477
478 pinctrl_dhcom_c: dhcom-c-grp {
479 fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>;
480 };
481
482 pinctrl_dhcom_d: dhcom-d-grp {
483 fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>;
484 };
485
486 pinctrl_dhcom_e: dhcom-e-grp {
487 fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>;
488 };
489
490 pinctrl_dhcom_f: dhcom-f-grp {
491 fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
492 };
493
494 pinctrl_dhcom_g: dhcom-g-grp {
495 fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>;
496 };
497
498 pinctrl_dhcom_h: dhcom-h-grp {
499 fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>;
500 };
501
502 pinctrl_dhcom_i: dhcom-i-grp {
503 fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>;
504 };
505
506 pinctrl_dhcom_j: dhcom-j-grp {
507 fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>;
508 };
509
510 pinctrl_dhcom_k: dhcom-k-grp {
511 fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>;
512 };
513
514 pinctrl_dhcom_l: dhcom-l-grp {
515 fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>;
516 };
517
518 pinctrl_dhcom_m: dhcom-m-grp {
519 fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>;
520 };
521
522 pinctrl_dhcom_n: dhcom-n-grp {
523 fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>;
524 };
525
526 pinctrl_dhcom_o: dhcom-o-grp {
527 fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;
528 };
529
530 pinctrl_dhcom_p: dhcom-p-grp {
531 fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>;
532 };
533
534 pinctrl_dhcom_q: dhcom-q-grp {
535 fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>;
536 };
537
538 pinctrl_dhcom_r: dhcom-r-grp {
539 fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>;
540 };
541
542 pinctrl_dhcom_s: dhcom-s-grp {
543 fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>;
544 };
545
546 pinctrl_dhcom_t: dhcom-t-grp {
547 fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>;
548 };
549
550 pinctrl_dhcom_u: dhcom-u-grp {
551 fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>;
552 };
553
554 pinctrl_dhcom_v: dhcom-v-grp {
555 fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>;
556 };
557
558 pinctrl_dhcom_w: dhcom-w-grp {
559 fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>;
560 };
561
562 pinctrl_dhcom_int: dhcom-int-grp {
563 fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>;
564 };
565
566 pinctrl_ecspi1: ecspi1-grp {
567 fsl,pins = <
568 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
569 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
570 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
571 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
572 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
573 >;
574 };
575
576 pinctrl_ecspi2: ecspi2-grp {
577 fsl,pins = <
578 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
579 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
580 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
581 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
582 >;
583 };
584
585 pinctrl_enet_100M: enet-100M-grp {
586 fsl,pins = <
587 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
588 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
589 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
590 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
591 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
592 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
593 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
594 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
595 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
596 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
597 >;
598 };
599
600 pinctrl_enet_vio: enet-vio-grp {
601 fsl,pins = <
602 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
603 >;
604 };
605
606 pinctrl_ethphy0: ethphy0-grp {
607 fsl,pins = <
608 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */
609 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */
610 >;
611 };
612
613 pinctrl_flexcan1: flexcan1-grp {
614 fsl,pins = <
615 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
616 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
617 >;
618 };
619
620 pinctrl_flexcan2: flexcan2-grp {
621 fsl,pins = <
622 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
623 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
624 >;
625 };
626
627 pinctrl_i2c1: i2c1-grp {
628 fsl,pins = <
629 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
630 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
631 >;
632 };
633
634 pinctrl_i2c1_gpio: i2c1-gpio-grp {
635 fsl,pins = <
636 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
637 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
638 >;
639 };
640
641 pinctrl_i2c2: i2c2-grp {
642 fsl,pins = <
643 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
644 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
645 >;
646 };
647
648 pinctrl_i2c2_gpio: i2c2-gpio-grp {
649 fsl,pins = <
650 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
651 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
652 >;
653 };
654
655 pinctrl_i2c3: i2c3-grp {
656 fsl,pins = <
657 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
658 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
659 >;
660 };
661
662 pinctrl_i2c3_gpio: i2c3-gpio-grp {
663 fsl,pins = <
664 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
665 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
666 >;
667 };
668
669 pinctrl_pcie: pcie-grp {
670 fsl,pins = <
671 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
672 >;
673 };
674
675 pinctrl_pmic: pmic-grp {
676 fsl,pins = <
677 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
678 >;
679 };
680
681 pinctrl_pwm1: pwm1-grp {
682 fsl,pins = <
683 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
684 >;
685 };
686
687 pinctrl_rtc: rtc-grp {
688 fsl,pins = <
689 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0
690 >;
691 };
692
693 pinctrl_tsc2004: tsc2004-grp {
694 fsl,pins = <
695 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0
696 >;
697 };
698
699 pinctrl_uart1: uart1-grp {
700 fsl,pins = <
701 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
702 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
703 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
704 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
705 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
706 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
707 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
708 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
709 >;
710 };
711
712 pinctrl_uart4: uart4-grp {
713 fsl,pins = <
714 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
715 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
716 >;
717 };
718
719 pinctrl_uart5: uart5-grp {
720 fsl,pins = <
721 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
722 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
723 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
724 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
725 >;
726 };
727
728 pinctrl_usbh1: usbh1-grp {
729 fsl,pins = <
730 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
731 >;
732 };
733
734 pinctrl_usbotg: usbotg-grp {
735 fsl,pins = <
736 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
737 >;
738 };
739
740 pinctrl_usdhc2: usdhc2-grp {
741 fsl,pins = <
742 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0
743 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
744 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
745 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
746 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
747 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
748 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
749 >;
750 };
751
752 pinctrl_usdhc3: usdhc3-grp {
753 fsl,pins = <
754 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
755 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
756 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
757 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
758 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
759 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
760 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0
761 >;
762 };
763
764 pinctrl_usdhc4: usdhc4-grp {
765 fsl,pins = <
766 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
767 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
768 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
769 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
770 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
771 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
772 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
773 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
774 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
775 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
776 >;
777 };
778
779 pinctrl_weim: weim-grp {
780 fsl,pins = <
781 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6
782 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6
783 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6
784 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6
785 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6
786 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6
787 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6
788 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6
789 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6
790 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6
791 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6
792 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6
793 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6
794 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6
795 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6
796 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6
797 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
798 MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */
799 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6
800 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */
801 >;
802 };
803
804 pinctrl_weim_cs0: weim-cs0-grp {
805 fsl,pins = <
806 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
807 >;
808 };
809
810 pinctrl_weim_cs1: weim-cs1-grp {
811 fsl,pins = <
812 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
813 >;
814 };
815};