blob: 35ec1a8df870f371abc61f35fcde6919d4b159a5 [file] [log] [blame]
Paul Barkera27d9f62021-07-12 21:14:09 +01001// SPDX-License-Identifier: GPL-2.0-only
Simon Glassb37e8152014-06-02 22:04:55 -06002/*
Paul Barkera27d9f62021-07-12 21:14:09 +01003 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
Simon Glassb37e8152014-06-02 22:04:55 -06004 */
5
6/ {
Simon Glassb37e8152014-06-02 22:04:55 -06007 cpus {
8 cpu@0 {
9 cpu0-supply = <&dcdc2_reg>;
10 };
11 };
12
Paul Barkera27d9f62021-07-12 21:14:09 +010013 memory@80000000 {
14 device_type = "memory";
15 reg = <0x80000000 0x10000000>; /* 256 MB */
16 };
17
Lokesh Vutlae302aa12016-05-16 11:24:25 +053018 chosen {
19 stdout-path = &uart0;
20 tick-timer = &timer2;
21 };
22
Tom Rini5ba15962015-07-31 19:55:08 -040023 leds {
Simon Glassb37e8152014-06-02 22:04:55 -060024 pinctrl-names = "default";
Tom Rini5ba15962015-07-31 19:55:08 -040025 pinctrl-0 = <&user_leds_s0>;
Simon Glassb37e8152014-06-02 22:04:55 -060026
Tom Rini5ba15962015-07-31 19:55:08 -040027 compatible = "gpio-leds";
Simon Glassb37e8152014-06-02 22:04:55 -060028
Paul Barkera27d9f62021-07-12 21:14:09 +010029 led2 {
Tom Rini5ba15962015-07-31 19:55:08 -040030 label = "beaglebone:green:heartbeat";
31 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
32 linux,default-trigger = "heartbeat";
33 default-state = "off";
Simon Glassb37e8152014-06-02 22:04:55 -060034 };
35
Paul Barkera27d9f62021-07-12 21:14:09 +010036 led3 {
Tom Rini5ba15962015-07-31 19:55:08 -040037 label = "beaglebone:green:mmc0";
38 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
39 linux,default-trigger = "mmc0";
40 default-state = "off";
Simon Glassb37e8152014-06-02 22:04:55 -060041 };
42
Paul Barkera27d9f62021-07-12 21:14:09 +010043 led4 {
Tom Rini5ba15962015-07-31 19:55:08 -040044 label = "beaglebone:green:usr2";
45 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
46 linux,default-trigger = "cpu0";
47 default-state = "off";
Simon Glassb37e8152014-06-02 22:04:55 -060048 };
49
Paul Barkera27d9f62021-07-12 21:14:09 +010050 led5 {
Tom Rini5ba15962015-07-31 19:55:08 -040051 label = "beaglebone:green:usr3";
52 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
53 linux,default-trigger = "mmc1";
54 default-state = "off";
Simon Glassb37e8152014-06-02 22:04:55 -060055 };
Tom Rini5ba15962015-07-31 19:55:08 -040056 };
Simon Glassb37e8152014-06-02 22:04:55 -060057
Paul Barkera27d9f62021-07-12 21:14:09 +010058 vmmcsd_fixed: fixedregulator0 {
Tom Rini5ba15962015-07-31 19:55:08 -040059 compatible = "regulator-fixed";
60 regulator-name = "vmmcsd_fixed";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 };
64};
Simon Glassb37e8152014-06-02 22:04:55 -060065
Tom Rini5ba15962015-07-31 19:55:08 -040066&am33xx_pinmux {
67 pinctrl-names = "default";
68 pinctrl-0 = <&clkout2_pin>;
Simon Glassb37e8152014-06-02 22:04:55 -060069
Tom Rini5ba15962015-07-31 19:55:08 -040070 user_leds_s0: user_leds_s0 {
71 pinctrl-single,pins = <
Paul Barkera27d9f62021-07-12 21:14:09 +010072 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
73 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */
74 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */
75 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */
Tom Rini5ba15962015-07-31 19:55:08 -040076 >;
Simon Glassb37e8152014-06-02 22:04:55 -060077 };
78
Tom Rini5ba15962015-07-31 19:55:08 -040079 i2c0_pins: pinmux_i2c0_pins {
80 pinctrl-single,pins = <
Paul Barkera27d9f62021-07-12 21:14:09 +010081 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */
82 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */
Tom Rini5ba15962015-07-31 19:55:08 -040083 >;
84 };
Simon Glassb37e8152014-06-02 22:04:55 -060085
Tom Rini5ba15962015-07-31 19:55:08 -040086 i2c2_pins: pinmux_i2c2_pins {
87 pinctrl-single,pins = <
Paul Barkera27d9f62021-07-12 21:14:09 +010088 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */
89 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */
Tom Rini5ba15962015-07-31 19:55:08 -040090 >;
91 };
Simon Glassb37e8152014-06-02 22:04:55 -060092
Tom Rini5ba15962015-07-31 19:55:08 -040093 uart0_pins: pinmux_uart0_pins {
94 pinctrl-single,pins = <
Paul Barkera27d9f62021-07-12 21:14:09 +010095 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
96 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
Tom Rini5ba15962015-07-31 19:55:08 -040097 >;
98 };
Simon Glassb37e8152014-06-02 22:04:55 -060099
Tom Rini5ba15962015-07-31 19:55:08 -0400100 clkout2_pin: pinmux_clkout2_pin {
101 pinctrl-single,pins = <
Paul Barkera27d9f62021-07-12 21:14:09 +0100102 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
Tom Rini5ba15962015-07-31 19:55:08 -0400103 >;
104 };
Simon Glassb37e8152014-06-02 22:04:55 -0600105
Tom Rini5ba15962015-07-31 19:55:08 -0400106 cpsw_default: cpsw_default {
107 pinctrl-single,pins = <
108 /* Slave 1 */
Paul Barkera27d9f62021-07-12 21:14:09 +0100109 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
110 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
111 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
112 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
113 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
114 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
115 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
116 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
117 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
118 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
119 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
120 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
121 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
Tom Rini5ba15962015-07-31 19:55:08 -0400122 >;
123 };
Simon Glassb37e8152014-06-02 22:04:55 -0600124
Tom Rini5ba15962015-07-31 19:55:08 -0400125 cpsw_sleep: cpsw_sleep {
126 pinctrl-single,pins = <
127 /* Slave 1 reset value */
Paul Barkera27d9f62021-07-12 21:14:09 +0100128 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
129 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
130 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
131 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
132 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
133 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
134 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
135 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
136 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
137 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
138 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
139 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
140 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
Tom Rini5ba15962015-07-31 19:55:08 -0400141 >;
142 };
Simon Glassb37e8152014-06-02 22:04:55 -0600143
Tom Rini5ba15962015-07-31 19:55:08 -0400144 davinci_mdio_default: davinci_mdio_default {
145 pinctrl-single,pins = <
146 /* MDIO */
Paul Barkera27d9f62021-07-12 21:14:09 +0100147 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
148 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
Tom Rini5ba15962015-07-31 19:55:08 -0400149 >;
150 };
Simon Glassb37e8152014-06-02 22:04:55 -0600151
Tom Rini5ba15962015-07-31 19:55:08 -0400152 davinci_mdio_sleep: davinci_mdio_sleep {
153 pinctrl-single,pins = <
154 /* MDIO reset value */
Paul Barkera27d9f62021-07-12 21:14:09 +0100155 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
156 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
Tom Rini5ba15962015-07-31 19:55:08 -0400157 >;
158 };
Simon Glassb37e8152014-06-02 22:04:55 -0600159
Tom Rini5ba15962015-07-31 19:55:08 -0400160 mmc1_pins: pinmux_mmc1_pins {
161 pinctrl-single,pins = <
Paul Barkera27d9f62021-07-12 21:14:09 +0100162 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */
163 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
164 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
165 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
166 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
167 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
168 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
Tom Rini5ba15962015-07-31 19:55:08 -0400169 >;
170 };
171
172 emmc_pins: pinmux_emmc_pins {
173 pinctrl-single,pins = <
Paul Barkera27d9f62021-07-12 21:14:09 +0100174 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
175 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
176 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
177 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
178 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
179 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
180 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
181 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
182 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
183 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
Tom Rini5ba15962015-07-31 19:55:08 -0400184 >;
185 };
186};
187
188&uart0 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&uart0_pins>;
Simon Glassb37e8152014-06-02 22:04:55 -0600191
Tom Rini5ba15962015-07-31 19:55:08 -0400192 status = "okay";
193};
Simon Glassb37e8152014-06-02 22:04:55 -0600194
Tom Rini5ba15962015-07-31 19:55:08 -0400195&usb0 {
Tom Rini5ba15962015-07-31 19:55:08 -0400196 dr_mode = "peripheral";
Paul Barkera27d9f62021-07-12 21:14:09 +0100197 interrupts-extended = <&intc 18 &tps 0>;
198 interrupt-names = "mc", "vbus";
Tom Rini5ba15962015-07-31 19:55:08 -0400199};
200
201&usb1 {
Tom Rini5ba15962015-07-31 19:55:08 -0400202 dr_mode = "host";
203};
204
Tom Rini5ba15962015-07-31 19:55:08 -0400205&i2c0 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&i2c0_pins>;
208
209 status = "okay";
210 clock-frequency = <400000>;
211
212 tps: tps@24 {
213 reg = <0x24>;
214 };
215
216 baseboard_eeprom: baseboard_eeprom@50 {
Paul Barkera27d9f62021-07-12 21:14:09 +0100217 compatible = "atmel,24c256";
Tom Rini5ba15962015-07-31 19:55:08 -0400218 reg = <0x50>;
219
220 #address-cells = <1>;
221 #size-cells = <1>;
222 baseboard_data: baseboard_data@0 {
223 reg = <0 0x100>;
Simon Glassb37e8152014-06-02 22:04:55 -0600224 };
225 };
Tom Rini5ba15962015-07-31 19:55:08 -0400226};
Simon Glassb37e8152014-06-02 22:04:55 -0600227
Tom Rini5ba15962015-07-31 19:55:08 -0400228&i2c2 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&i2c2_pins>;
Simon Glassb37e8152014-06-02 22:04:55 -0600231
Tom Rini5ba15962015-07-31 19:55:08 -0400232 status = "okay";
233 clock-frequency = <100000>;
Simon Glassb37e8152014-06-02 22:04:55 -0600234
Tom Rini5ba15962015-07-31 19:55:08 -0400235 cape_eeprom0: cape_eeprom0@54 {
Paul Barkera27d9f62021-07-12 21:14:09 +0100236 compatible = "atmel,24c256";
Tom Rini5ba15962015-07-31 19:55:08 -0400237 reg = <0x54>;
238 #address-cells = <1>;
239 #size-cells = <1>;
240 cape0_data: cape_data@0 {
241 reg = <0 0x100>;
Simon Glassb37e8152014-06-02 22:04:55 -0600242 };
Tom Rini5ba15962015-07-31 19:55:08 -0400243 };
Simon Glassb37e8152014-06-02 22:04:55 -0600244
Tom Rini5ba15962015-07-31 19:55:08 -0400245 cape_eeprom1: cape_eeprom1@55 {
Paul Barkera27d9f62021-07-12 21:14:09 +0100246 compatible = "atmel,24c256";
Tom Rini5ba15962015-07-31 19:55:08 -0400247 reg = <0x55>;
248 #address-cells = <1>;
249 #size-cells = <1>;
250 cape1_data: cape_data@0 {
251 reg = <0 0x100>;
Simon Glassb37e8152014-06-02 22:04:55 -0600252 };
Tom Rini5ba15962015-07-31 19:55:08 -0400253 };
Simon Glassb37e8152014-06-02 22:04:55 -0600254
Tom Rini5ba15962015-07-31 19:55:08 -0400255 cape_eeprom2: cape_eeprom2@56 {
Paul Barkera27d9f62021-07-12 21:14:09 +0100256 compatible = "atmel,24c256";
Tom Rini5ba15962015-07-31 19:55:08 -0400257 reg = <0x56>;
258 #address-cells = <1>;
259 #size-cells = <1>;
260 cape2_data: cape_data@0 {
261 reg = <0 0x100>;
Simon Glassb37e8152014-06-02 22:04:55 -0600262 };
Tom Rini5ba15962015-07-31 19:55:08 -0400263 };
Simon Glassb37e8152014-06-02 22:04:55 -0600264
Tom Rini5ba15962015-07-31 19:55:08 -0400265 cape_eeprom3: cape_eeprom3@57 {
Paul Barkera27d9f62021-07-12 21:14:09 +0100266 compatible = "atmel,24c256";
Tom Rini5ba15962015-07-31 19:55:08 -0400267 reg = <0x57>;
268 #address-cells = <1>;
269 #size-cells = <1>;
270 cape3_data: cape_data@0 {
271 reg = <0 0x100>;
Simon Glassb37e8152014-06-02 22:04:55 -0600272 };
273 };
274};
275
Tom Rini5ba15962015-07-31 19:55:08 -0400276
Simon Glassb37e8152014-06-02 22:04:55 -0600277/include/ "tps65217.dtsi"
278
279&tps {
Tom Rini5ba15962015-07-31 19:55:08 -0400280 /*
281 * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
282 * mode") at poweroff. Most BeagleBone versions do not support RTC-only
283 * mode and risk hardware damage if this mode is entered.
284 *
285 * For details, see linux-omap mailing list May 2015 thread
286 * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
287 * In particular, messages:
288 * http://www.spinics.net/lists/linux-omap/msg118585.html
289 * http://www.spinics.net/lists/linux-omap/msg118615.html
290 *
291 * You can override this later with
292 * &tps { /delete-property/ ti,pmic-shutdown-controller; }
293 * if you want to use RTC-only mode and made sure you are not affected
294 * by the hardware problems. (Tip: double-check by performing a current
295 * measurement after shutdown: it should be less than 1 mA.)
296 */
Paul Barkera27d9f62021-07-12 21:14:09 +0100297
298 interrupts = <7>; /* NMI */
299 interrupt-parent = <&intc>;
300
Tom Rini5ba15962015-07-31 19:55:08 -0400301 ti,pmic-shutdown-controller;
302
Paul Barkera27d9f62021-07-12 21:14:09 +0100303 charger {
304 status = "okay";
305 };
306
307 pwrbutton {
308 status = "okay";
309 };
310
Simon Glassb37e8152014-06-02 22:04:55 -0600311 regulators {
312 dcdc1_reg: regulator@0 {
Tom Rini5ba15962015-07-31 19:55:08 -0400313 regulator-name = "vdds_dpr";
Simon Glassb37e8152014-06-02 22:04:55 -0600314 regulator-always-on;
315 };
316
317 dcdc2_reg: regulator@1 {
318 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
319 regulator-name = "vdd_mpu";
320 regulator-min-microvolt = <925000>;
Paul Barkera27d9f62021-07-12 21:14:09 +0100321 regulator-max-microvolt = <1351500>;
Simon Glassb37e8152014-06-02 22:04:55 -0600322 regulator-boot-on;
323 regulator-always-on;
324 };
325
326 dcdc3_reg: regulator@2 {
327 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
328 regulator-name = "vdd_core";
329 regulator-min-microvolt = <925000>;
330 regulator-max-microvolt = <1150000>;
331 regulator-boot-on;
332 regulator-always-on;
333 };
334
335 ldo1_reg: regulator@3 {
Tom Rini5ba15962015-07-31 19:55:08 -0400336 regulator-name = "vio,vrtc,vdds";
Simon Glassb37e8152014-06-02 22:04:55 -0600337 regulator-always-on;
338 };
339
340 ldo2_reg: regulator@4 {
Tom Rini5ba15962015-07-31 19:55:08 -0400341 regulator-name = "vdd_3v3aux";
Simon Glassb37e8152014-06-02 22:04:55 -0600342 regulator-always-on;
343 };
344
345 ldo3_reg: regulator@5 {
Tom Rini5ba15962015-07-31 19:55:08 -0400346 regulator-name = "vdd_1v8";
Simon Glassb37e8152014-06-02 22:04:55 -0600347 regulator-always-on;
348 };
349
350 ldo4_reg: regulator@6 {
Tom Rini5ba15962015-07-31 19:55:08 -0400351 regulator-name = "vdd_3v3a";
Simon Glassb37e8152014-06-02 22:04:55 -0600352 regulator-always-on;
353 };
354 };
355};
356
357&cpsw_emac0 {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300358 phy-handle = <&ethphy0>;
Simon Glassb37e8152014-06-02 22:04:55 -0600359 phy-mode = "mii";
360};
361
Simon Glassb37e8152014-06-02 22:04:55 -0600362&mac {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300363 slaves = <1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600364 pinctrl-names = "default", "sleep";
365 pinctrl-0 = <&cpsw_default>;
366 pinctrl-1 = <&cpsw_sleep>;
Tom Rini5ba15962015-07-31 19:55:08 -0400367 status = "okay";
Simon Glassb37e8152014-06-02 22:04:55 -0600368};
369
370&davinci_mdio {
371 pinctrl-names = "default", "sleep";
372 pinctrl-0 = <&davinci_mdio_default>;
373 pinctrl-1 = <&davinci_mdio_sleep>;
Tom Rini5ba15962015-07-31 19:55:08 -0400374 status = "okay";
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300375
376 ethphy0: ethernet-phy@0 {
377 reg = <0>;
378 };
Tom Rini5ba15962015-07-31 19:55:08 -0400379};
380
381&mmc1 {
382 status = "okay";
383 bus-width = <0x4>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&mmc1_pins>;
Mugunthan V N4bbfcc32016-05-16 11:24:27 +0530386 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
Tom Rini5ba15962015-07-31 19:55:08 -0400387};
388
389&aes {
390 status = "okay";
391};
392
393&sham {
394 status = "okay";
Simon Glassb37e8152014-06-02 22:04:55 -0600395};
Dario Binacchi95657952021-06-02 22:38:03 +0200396
397&rtc {
398 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
399 clock-names = "ext-clk", "int-clk";
400};