Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / ab74a3e5fce0bd786c12d375d13e268240d46aae / . / arch / arm / dts / imx8mn-evk.dtsi
blob: ed865444da54c0c403bfa885e1fc527c30720717 [file] [log] [blame]
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart2;
12 };
13
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
18
19 status {
20 label = "yellow:status";
21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on";
23 };
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0x0 0x40000000 0 0x80000000>;
29 };
30
31 reg_usdhc2_vmmc: regulator-usdhc2 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35 regulator-name = "VSD_3V3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39 enable-active-high;
40 };
41
42 ir-receiver {
43 compatible = "gpio-ir-receiver";
44 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ir>;
47 linux,autosuspend-period = <125>;
48 };
49};
50
51&fec1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_fec1>;
54 phy-mode = "rgmii-id";
55 phy-handle = <&ethphy0>;
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]56 fsl,magic-packet;
57 status = "okay";
58
59 mdio {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 ethphy0: ethernet-phy@0 {
64 compatible = "ethernet-phy-ieee802.3-c22";
65 reg = <0>;
Heiko Thieryab74a3e2022-02-23 10:48:26 +0100[diff] [blame^]66 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
67 reset-assert-us = <10000>;
Heiko Thiery26eaca62022-02-23 09:10:29 +0100[diff] [blame]68 vddio-supply = <&vddio>;
69
70 vddio: vddio-regulator {
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
73 };
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]74 };
75 };
76};
77
78&i2c1 {
79 clock-frequency = <400000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_i2c1>;
82 status = "okay";
83};
84
85&i2c2 {
86 clock-frequency = <400000>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_i2c2>;
89 status = "okay";
90
91 ptn5110: tcpc@50 {
92 compatible = "nxp,ptn5110";
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_typec1>;
95 reg = <0x50>;
96 interrupt-parent = <&gpio2>;
97 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
98 status = "okay";
99
100 port {
101 typec1_dr_sw: endpoint {
102 remote-endpoint = <&usb1_drd_sw>;
103 };
104 };
105
106 typec1_con: connector {
107 compatible = "usb-c-connector";
108 label = "USB-C";
109 power-role = "dual";
110 data-role = "dual";
111 try-power-role = "sink";
112 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
113 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
114 PDO_VAR(5000, 20000, 3000)>;
115 op-sink-microwatt = <15000000>;
116 self-powered;
117 };
118 };
119};
120
121&i2c3 {
122 clock-frequency = <400000>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_i2c3>;
125 status = "okay";
126
127 pca6416: gpio@20 {
128 compatible = "ti,tca6416";
129 reg = <0x20>;
130 gpio-controller;
131 #gpio-cells = <2>;
132 };
133};
134
135&snvs_pwrkey {
136 status = "okay";
137};
138
139&uart2 { /* console */
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_uart2>;
142 status = "okay";
143};
144
145&usbotg1 {
146 dr_mode = "otg";
147 hnp-disable;
148 srp-disable;
149 adp-disable;
150 usb-role-switch;
151 samsung,picophy-pre-emp-curr-control = <3>;
152 samsung,picophy-dc-vol-level-adjust = <7>;
153 status = "okay";
154
155 port {
156 usb1_drd_sw: endpoint {
157 remote-endpoint = <&typec1_dr_sw>;
158 };
159 };
160};
161
162&usdhc2 {
163 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
164 assigned-clock-rates = <200000000>;
165 pinctrl-names = "default", "state_100mhz", "state_200mhz";
166 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
167 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
168 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
169 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
170 bus-width = <4>;
171 vmmc-supply = <&reg_usdhc2_vmmc>;
172 status = "okay";
173};
174
175&usdhc3 {
176 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
177 assigned-clock-rates = <400000000>;
178 pinctrl-names = "default", "state_100mhz", "state_200mhz";
179 pinctrl-0 = <&pinctrl_usdhc3>;
180 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
181 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
182 bus-width = <8>;
183 non-removable;
184 status = "okay";
185};
186
187&wdog1 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_wdog>;
190 fsl,ext-reset-output;
191 status = "okay";
192};
193
194&iomuxc {
195 pinctrl_fec1: fec1grp {
196 fsl,pins = <
197 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
198 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
199 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
200 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
201 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
202 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
203 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
204 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
205 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
206 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
207 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
208 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
209 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
210 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
211 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
212 >;
213 };
214
215 pinctrl_gpio_led: gpioledgrp {
216 fsl,pins = <
217 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
218 >;
219 };
220
221 pinctrl_ir: irgrp {
222 fsl,pins = <
223 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
224 >;
225 };
226
227 pinctrl_i2c1: i2c1grp {
228 fsl,pins = <
229 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
230 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
231 >;
232 };
233
234 pinctrl_i2c2: i2c2grp {
235 fsl,pins = <
236 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
237 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
238 >;
239 };
240
241 pinctrl_i2c3: i2c3grp {
242 fsl,pins = <
243 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
244 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
245 >;
246 };
247
248 pinctrl_pmic: pmicirqgrp {
249 fsl,pins = <
250 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
251 >;
252 };
253
254 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
255 fsl,pins = <
256 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
257 >;
258 };
259
260 pinctrl_typec1: typec1grp {
261 fsl,pins = <
262 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
263 >;
264 };
265
266 pinctrl_uart2: uart2grp {
267 fsl,pins = <
268 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
269 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
270 >;
271 };
272
273 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
274 fsl,pins = <
275 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
276 >;
277 };
278
279 pinctrl_usdhc2: usdhc2grp {
280 fsl,pins = <
281 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
282 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
283 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
284 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
285 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
286 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
287 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
288 >;
289 };
290
291 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
292 fsl,pins = <
293 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
294 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
295 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
296 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
297 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
298 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
299 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
300 >;
301 };
302
303 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
304 fsl,pins = <
305 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
306 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
307 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
308 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
309 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
310 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
311 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
312 >;
313 };
314
315 pinctrl_usdhc3: usdhc3grp {
316 fsl,pins = <
317 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
318 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
319 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
320 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
321 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
322 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
323 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
324 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
325 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
326 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
327 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
328 >;
329 };
330
331 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
332 fsl,pins = <
333 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
334 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
335 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
336 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
337 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
338 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
339 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
340 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
341 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
342 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
343 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
344 >;
345 };
346
347 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
348 fsl,pins = <
349 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
350 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
351 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
352 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
353 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
354 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
355 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
356 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
357 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
358 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
359 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
360 >;
361 };
362
363 pinctrl_wdog: wdoggrp {
364 fsl,pins = <
365 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
366 >;
367 };
368};