| Lei Wen | 4301303 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011 |
| 3 | * Marvell Semiconductor <www.marvell.com> |
| 4 | * Written-by: Lei Wen <leiwen@marvell.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 22 | * MA 02110-1301 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef _PANTHEON_H |
| 26 | #define _PANTHEON_H |
| 27 | |
| 28 | #ifndef __ASSEMBLY__ |
| 29 | #include <asm/types.h> |
| 30 | #include <asm/io.h> |
| 31 | #endif /* __ASSEMBLY__ */ |
| 32 | |
| 33 | #include <asm/arch/cpu.h> |
| 34 | |
| 35 | /* Common APB clock register bit definitions */ |
| 36 | #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ |
| 37 | #define APBC_FNCLK (1<<1) /* Functional Clock Enable */ |
| 38 | #define APBC_RST (1<<2) /* Reset Generation */ |
| 39 | /* Functional Clock Selection Mask */ |
| 40 | #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) |
| 41 | |
| 42 | /* Register Base Addresses */ |
| 43 | #define PANTHEON_DRAM_BASE 0xB0000000 |
| 44 | #define PANTHEON_TIMER_BASE 0xD4014000 |
| 45 | #define PANTHEON_WD_TIMER_BASE 0xD4080000 |
| 46 | #define PANTHEON_APBC_BASE 0xD4015000 |
| 47 | #define PANTHEON_UART1_BASE 0xD4017000 |
| 48 | #define PANTHEON_UART2_BASE 0xD4018000 |
| 49 | #define PANTHEON_GPIO_BASE 0xD4019000 |
| 50 | #define PANTHEON_MFPR_BASE 0xD401E000 |
| 51 | #define PANTHEON_MPMU_BASE 0xD4050000 |
| 52 | #define PANTHEON_CPU_BASE 0xD4282C00 |
| 53 | |
| 54 | #endif /* _PANTHEON_H */ |