| Matthias Weisser | 63c36f5 | 2010-08-09 13:31:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Matthias Weisser <weisserm@arcor.de> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef ASM_OFFSETS_H |
| 25 | #define ASM_OFFSETS_H |
| 26 | |
| 27 | /* |
| 28 | * Offset definitions for DDR controller |
| 29 | */ |
| 30 | #define DDR2_DRIC 0x00 |
| 31 | #define DDR2_DRIC1 0x02 |
| 32 | #define DDR2_DRIC2 0x04 |
| 33 | #define DDR2_DRCA 0x06 |
| 34 | #define DDR2_DRCM 0x08 |
| 35 | #define DDR2_DRCST1 0x0a |
| 36 | #define DDR2_DRCST2 0x0c |
| 37 | #define DDR2_DRCR 0x0e |
| 38 | #define DDR2_DRCF 0x20 |
| 39 | #define DDR2_DRASR 0x30 |
| 40 | #define DDR2_DRIMS 0x50 |
| 41 | #define DDR2_DROS 0x60 |
| 42 | #define DDR2_DRIBSODT1 0x64 |
| 43 | #define DDR2_DROABA 0x70 |
| 44 | #define DDR2_DROBS 0x84 |
| 45 | |
| 46 | /* |
| 47 | * Offset definitions Chip Control Module |
| 48 | */ |
| 49 | #define CCNT_CDCRC 0xec |
| 50 | |
| 51 | /* |
| 52 | * Offset definitions clock reset generator |
| 53 | */ |
| 54 | #define CRG_CRPR 0x00 |
| 55 | #define CRG_CRHA 0x18 |
| 56 | #define CRG_CRPA 0x1c |
| 57 | #define CRG_CRPB 0x20 |
| 58 | #define CRG_CRHB 0x24 |
| 59 | #define CRG_CRAM 0x28 |
| 60 | |
| 61 | /* |
| 62 | * Offset definitions External bus interface |
| 63 | */ |
| 64 | #define MEMC_MCFMODE0 0x00 |
| 65 | #define MEMC_MCFMODE2 0x08 |
| 66 | #define MEMC_MCFMODE4 0x10 |
| 67 | #define MEMC_MCFTIM0 0x20 |
| 68 | #define MEMC_MCFTIM2 0x28 |
| 69 | #define MEMC_MCFTIM4 0x30 |
| 70 | #define MEMC_MCFAREA0 0x40 |
| 71 | #define MEMC_MCFAREA2 0x48 |
| 72 | #define MEMC_MCFAREA4 0x50 |
| 73 | |
| 74 | #endif /* ASM_OFFSETS_H */ |