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Graeme Russ78972ea2009-08-23 12:59:58 +10001/*
Graeme Russ45fc1d82011-04-13 19:43:26 +10002 * (C) Copyright 2008,2009
3 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russ78972ea2009-08-23 12:59:58 +10004 *
5 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02006 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
Graeme Russ78972ea2009-08-23 12:59:58 +10007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
Graeme Russ45fc1d82011-04-13 19:43:26 +100026
Graeme Russ78972ea2009-08-23 12:59:58 +100027#include <common.h>
28#include <pci.h>
29#include <asm/pci.h>
Graeme Russ0d992d02011-08-04 22:05:09 +100030#include <asm/arch/pci.h>
Graeme Russ78972ea2009-08-23 12:59:58 +100031
32static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
33{
34 /* a configurable lists of IRQs to steal when we need one */
35 static int irq_list[] = {
36 CONFIG_SYS_FIRST_PCI_IRQ,
37 CONFIG_SYS_SECOND_PCI_IRQ,
38 CONFIG_SYS_THIRD_PCI_IRQ,
39 CONFIG_SYS_FORTH_PCI_IRQ
40 };
Graeme Russf3f8b012011-11-08 02:33:16 +000041 static int next_irq_index;
Graeme Russ78972ea2009-08-23 12:59:58 +100042
43 uchar tmp_pin;
44 int pin;
45
46 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
47 pin = tmp_pin;
48
49 pin -= 1; /* PCI config space use 1-based numbering */
Graeme Russf3f8b012011-11-08 02:33:16 +000050 if (pin == -1)
Graeme Russ78972ea2009-08-23 12:59:58 +100051 return; /* device use no irq */
Graeme Russ78972ea2009-08-23 12:59:58 +100052
53 /* map device number + pin to a pin on the sc520 */
54 switch (PCI_DEV(dev)) {
55 case 12: /* First Ethernet Chip */
56 pin += SC520_PCI_INTA;
57 break;
58
59 case 13: /* Second Ethernet Chip */
60 pin += SC520_PCI_INTB;
61 break;
62
63 default:
64 return;
65 }
66
67 pin &= 3; /* wrap around */
68
69 if (sc520_pci_ints[pin] == -1) {
70 /* re-route one interrupt for us */
Graeme Russf3f8b012011-11-08 02:33:16 +000071 if (next_irq_index > 3)
Graeme Russ78972ea2009-08-23 12:59:58 +100072 return;
Graeme Russf3f8b012011-11-08 02:33:16 +000073
74 if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
Graeme Russ78972ea2009-08-23 12:59:58 +100075 return;
Graeme Russf3f8b012011-11-08 02:33:16 +000076
Graeme Russ78972ea2009-08-23 12:59:58 +100077 next_irq_index++;
78 }
79
Graeme Russf3f8b012011-11-08 02:33:16 +000080 if (-1 != sc520_pci_ints[pin])
81 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
Graeme Russ78972ea2009-08-23 12:59:58 +100082 sc520_pci_ints[pin]);
Graeme Russf3f8b012011-11-08 02:33:16 +000083
Graeme Russ78972ea2009-08-23 12:59:58 +100084 printf("fixup_irq: device %d pin %c irq %d\n",
85 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
86}
87
88static struct pci_controller enet_hose = {
89 fixup_irq: pci_enet_fixup_irq,
90};
91
92void pci_init_board(void)
93{
94 pci_sc520_init(&enet_hose);
95}
Graeme Russ6a554572010-04-24 00:05:54 +100096
97int pci_set_regions(struct pci_controller *hose)
98{
99 /* System memory space */
100 pci_set_region(hose->regions + 0,
101 SC520_PCI_MEMORY_BUS,
102 SC520_PCI_MEMORY_PHYS,
103 SC520_PCI_MEMORY_SIZE,
104 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
105
106 /* ISA/PCI memory space */
107 pci_set_region(hose->regions + 1,
108 SC520_ISA_MEM_BUS,
109 SC520_ISA_MEM_PHYS,
110 SC520_ISA_MEM_SIZE,
111 PCI_REGION_MEM);
112
113 /* PCI I/O space */
114 pci_set_region(hose->regions + 2,
115 SC520_PCI_IO_BUS,
116 SC520_PCI_IO_PHYS,
117 SC520_PCI_IO_SIZE,
118 PCI_REGION_IO);
119
120 /* ISA/PCI I/O space */
121 pci_set_region(hose->regions + 3,
122 SC520_ISA_IO_BUS,
123 SC520_ISA_IO_PHYS,
124 SC520_ISA_IO_SIZE,
125 PCI_REGION_IO);
126
127 return 4;
128}