Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 35b130c3b62e097a6f3fa242f572544d2033c1f2 / . / drivers / block / mxc_ata.c
blob: 35bc656dd74a236d24a4c2586b349b664ba720e1 [file] [log] [blame]
Marek Vasute2801482011-01-13 07:27:55 +0000[diff] [blame]1/*
2 * Freescale iMX51 ATA driver
3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Based on code by:
7 * Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
8 *
9 * Based on code from original FSL ATA driver, which is
10 * part of eCos, the Embedded Configurable Operating System.
11 * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <command.h>
31#include <config.h>
32#include <asm/byteorder.h>
33#include <asm/io.h>
34#include <ide.h>
35
36#include <asm/arch/imx-regs.h>
37#include <asm/arch/clock.h>
38
39/* MXC ATA register offsets */
40struct mxc_ata_config_regs {
41 u8 time_off; /* 0x00 */
42 u8 time_on;
43 u8 time_1;
44 u8 time_2w;
45 u8 time_2r;
46 u8 time_ax;
47 u8 time_pio_rdx;
48 u8 time_4;
49 u8 time_9;
50 u8 time_m;
51 u8 time_jn;
52 u8 time_d;
53 u8 time_k;
54 u8 time_ack;
55 u8 time_env;
56 u8 time_udma_rdx;
57 u8 time_zah; /* 0x10 */
58 u8 time_mlix;
59 u8 time_dvh;
60 u8 time_dzfs;
61 u8 time_dvs;
62 u8 time_cvh;
63 u8 time_ss;
64 u8 time_cyc;
65 u32 fifo_data_32; /* 0x18 */
66 u32 fifo_data_16;
67 u32 fifo_fill;
68 u32 ata_control;
69 u32 interrupt_pending;
70 u32 interrupt_enable;
71 u32 interrupt_clear;
72 u32 fifo_alarm;
73};
74
75struct mxc_data_hdd_regs {
76 u32 drive_data; /* 0xa0 */
77 u32 drive_features;
78 u32 drive_sector_count;
79 u32 drive_sector_num;
80 u32 drive_cyl_low;
81 u32 drive_cyl_high;
82 u32 drive_dev_head;
83 u32 command;
84 u32 status;
85 u32 alt_status;
86};
87
88/* PIO timing table */
89#define NR_PIO_SPECS 5
Marek Vasute2801482011-01-13 07:27:55 +0000[diff] [blame]90static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 };
91static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 };
Marek Vasute2801482011-01-13 07:27:55 +0000[diff] [blame]92static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 };
93static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 };
94static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 };
95
96#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8)
97static void set_ata_bus_timing(unsigned char mode)
98{
Marek Vasute2801482011-01-13 07:27:55 +0000[diff] [blame]99 uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK);
100
101 struct mxc_ata_config_regs *ata_regs;
102 ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
103
104 if (mode >= NR_PIO_SPECS)
105 return;
106
107 /* Write TIME_OFF/ON/1/2W */
Marek Vasut801abe42011-09-23 00:04:49 +0000[diff] [blame]108 writeb(3, &ata_regs->time_off);
109 writeb(3, &ata_regs->time_on);
110 writeb((pio_t1[mode] + T) / T, &ata_regs->time_1);
111 writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w);
Marek Vasute2801482011-01-13 07:27:55 +0000[diff] [blame]112
113 /* Write TIME_2R/AX/RDX/4 */
Marek Vasut801abe42011-09-23 00:04:49 +0000[diff] [blame]114 writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r);
115 writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax);
116 writeb(1, &ata_regs->time_pio_rdx);
117 writeb((pio_t4[mode] + T) / T, &ata_regs->time_4);
Marek Vasute2801482011-01-13 07:27:55 +0000[diff] [blame]118
119 /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
Marek Vasut801abe42011-09-23 00:04:49 +0000[diff] [blame]120 writeb((pio_t9[mode] + T) / T, &ata_regs->time_9);
Marek Vasute2801482011-01-13 07:27:55 +0000[diff] [blame]121}
122
123int ide_preinit(void)
124{
125 struct mxc_ata_config_regs *ata_regs;
126 ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
127
128 /* 46.3.3.4 @ FSL iMX51 manual */
129 /* FIFO normal op., drive reset */
130 writel(0x80, &ata_regs->ata_control);
131 /* FIFO normal op., drive not reset */
132 writel(0xc0, &ata_regs->ata_control);
133
134 /* Configure the PIO timing */
135 set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE);
136
137 /* 46.3.3.4 @ FSL iMX51 manual */
138 /* Drive not reset, IORDY handshake */
139 writel(0x41, &ata_regs->ata_control);
140
141 return 0;
142}