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git01.mediatek.com / filogic / uboot / 3587d0b46c2cf93a8c7b0b15f4760960c18133b9 / . / arch / m68k / include / asm / m520x.h
blob: ce271eca91aabfede86d8417656cdf4234f4d595 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]2/*
3 * m520x.h -- Definitions for Freescale Coldfire 520x
4 *
5 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]7 */
8
9#ifndef __M520X__
10#define __M520X__
11
12/* *** System Control Module (SCM) *** */
13#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
14#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
15#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
16#define MPROT_MTR 4
17#define MPROT_MTW 2
18#define MPROT_MPL 1
19
20#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
21#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
22#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
23
24#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
25
26#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
27#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
28#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
29#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
30#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
31#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
32
33#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
34#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
35#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
36#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
37#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
38#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
39#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
40
41#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
42#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
43#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
44#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
45#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
46
47#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
48#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
49#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
50
51#define PACR_SP 4
52#define PACR_WP 2
53#define PACR_TP 1
54
55#define SCM_BMT_BME (0x00000008)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]56#define SCM_BMT_BMT(x) ((x) & 0x07)
57#define SCM_BMT_BMT1024 (0x0000)
58#define SCM_BMT_BMT512 (0x0001)
59#define SCM_BMT_BMT256 (0x0002)
60#define SCM_BMT_BMT128 (0x0003)
61#define SCM_BMT_BMT64 (0x0004)
62#define SCM_BMT_BMT32 (0x0005)
63#define SCM_BMT_BMT16 (0x0006)
64#define SCM_BMT_BMT8 (0x0007)
65
66#define SCM_CWCR_RO (0x8000)
67#define SCM_CWCR_CWR_WH (0x0100)
68#define SCM_CWCR_CWE (0x0080)
69#define SCM_CWRI_WINDOW (0x0060)
70#define SCM_CWRI_RESET (0x0040)
71#define SCM_CWRI_INT_RESET (0x0020)
72#define SCM_CWRI_INT (0x0000)
73#define SCM_CWCR_CWT(x) (((x) & 0x001F))
74
75#define SCM_ISR_CFEI (0x02)
76#define SCM_ISR_CWIC (0x01)
77
78#define SCM_CFIER_ECFEI (0x01)
79
80#define SCM_CFLOC_LOC (0x80)
81
82#define SCM_CFATR_WRITE (0x80)
83#define SCM_CFATR_SZ32 (0x20)
84#define SCM_CFATR_SZ16 (0x10)
85#define SCM_CFATR_SZ08 (0x00)
86#define SCM_CFATR_CACHE (0x08)
87#define SCM_CFATR_MODE (0x02)
88#define SCM_CFATR_TYPE (0x01)
89
90/* *** Interrupt Controller (INTC) *** */
91#define INT0_LO_RSVD0 (0)
92#define INT0_LO_EPORT_F1 (1)
93#define INT0_LO_EPORT_F4 (2)
94#define INT0_LO_EPORT_F7 (3)
95#define INT1_LO_PIT0 (4)
96#define INT1_LO_PIT1 (5)
97/* 6 - 7 rsvd */
98#define INT0_LO_EDMA_00 (8)
99#define INT0_LO_EDMA_01 (9)
100#define INT0_LO_EDMA_02 (10)
101#define INT0_LO_EDMA_03 (11)
102#define INT0_LO_EDMA_04 (12)
103#define INT0_LO_EDMA_05 (13)
104#define INT0_LO_EDMA_06 (14)
105#define INT0_LO_EDMA_07 (15)
106#define INT0_LO_EDMA_08 (16)
107#define INT0_LO_EDMA_09 (17)
108#define INT0_LO_EDMA_10 (18)
109#define INT0_LO_EDMA_11 (19)
110#define INT0_LO_EDMA_12 (20)
111#define INT0_LO_EDMA_13 (21)
112#define INT0_LO_EDMA_14 (22)
113#define INT0_LO_EDMA_15 (23)
114#define INT0_LO_EDMA_ERR (24)
115#define INT0_LO_SCM_CWIC (25)
116#define INT0_LO_UART0 (26)
117#define INT0_LO_UART1 (27)
118#define INT0_LO_UART2 (28)
119/* 29 rsvd */
120#define INT0_LO_I2C (30)
121#define INT0_LO_QSPI (31)
122
123#define INT0_HI_DTMR0 (32)
124#define INT0_HI_DTMR1 (33)
125#define INT0_HI_DTMR2 (34)
126#define INT0_HI_DTMR3 (35)
127#define INT0_HI_FEC0_TXF (36)
128#define INT0_HI_FEC0_TXB (37)
129#define INT0_HI_FEC0_UN (38)
130#define INT0_HI_FEC0_RL (39)
131#define INT0_HI_FEC0_RXF (40)
132#define INT0_HI_FEC0_RXB (41)
133#define INT0_HI_FEC0_MII (42)
134#define INT0_HI_FEC0_LC (43)
135#define INT0_HI_FEC0_HBERR (44)
136#define INT0_HI_FEC0_GRA (45)
137#define INT0_HI_FEC0_EBERR (46)
138#define INT0_HI_FEC0_BABT (47)
139#define INT0_HI_FEC0_BABR (48)
140/* 49 - 61 rsvd */
141#define INT0_HI_SCMISR_CFEI (62)
142
143/* *** Reset Controller Module (RCM) *** */
144#define RCM_RCR_SOFTRST (0x80)
145#define RCM_RCR_FRCRSTOUT (0x40)
146
147#define RCM_RSR_SOFT (0x20)
148#define RCM_RSR_WDOG (0x10)
149#define RCM_RSR_POR (0x08)
150#define RCM_RSR_EXT (0x04)
151#define RCM_RSR_WDR_CORE (0x02)
152#define RCM_RSR_LOL (0x01)
153
154/* *** Chip Configuration Module (CCM) *** */
155#define CCM_CCR_CSC (0x0200)
156#define CCM_CCR_OSCFREQ (0x0080)
157#define CCM_CCR_LIMP (0x0040)
158#define CCM_CCR_LOAD (0x0020)
159#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3)
160#define CCM_CCR_OSC_MODE (0x0004)
161#define CCM_CCR_PLL_MODE (0x0002)
162#define CCM_CCR_RESERVED (0x0001)
163
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]164#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]165#define CCM_CIR_PRN(x) ((x) & 0x003F)
166
167/* *** General Purpose I/O (GPIO) *** */
168#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F)
169#define GPIO_PDR_BE(x) ((x) & 0x0F)
170#define GPIO_PDR_CS(x) (((x) & 0x07) << 1)
171#define GPIO_PDR_FECI2C(x) ((x) & 0x0F)
172#define GPIO_PDR_QSPI(x) ((x) & 0x0F)
173#define GPIO_PDR_TIMER(x) ((x) & 0x0F)
174#define GPIO_PDR_UART(x) ((x) & 0xFF)
175#define GPIO_PDR_FECH(x) ((x) & 0xFF)
176#define GPIO_PDR_FECL(x) ((x) & 0xFF)
177
178#define GPIO_PAR_FBCTL_OE (0x10)
179#define GPIO_PAR_FBCTL_TA (0x08)
180#define GPIO_PAR_FBCTL_RWB (0x04)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]181#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]182#define GPIO_PAR_FBCTL_TS_TS (0x03)
183#define GPIO_PAR_FBCTL_TS_DMA (0x02)
184
185#define GPIO_PAR_BE3 (0x08)
186#define GPIO_PAR_BE2 (0x04)
187#define GPIO_PAR_BE1 (0x02)
188#define GPIO_PAR_BE0 (0x01)
189
190#define GPIO_PAR_CS3 (0x08)
191#define GPIO_PAR_CS2 (0x04)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]192#define GPIO_PAR_CS1_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]193#define GPIO_PAR_CS1_CS1 (0x03)
194#define GPIO_PAR_CS1_SDCS1 (0x02)
195
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]196#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F)
197#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]198#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
199#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
200#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]201#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]202#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
203#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
204#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]205#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0)
206#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]207#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
208#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]209#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]210#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
211#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
212
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]213#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]214#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
215#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
216#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]217#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]218#define GPIO_PAR_QSPI_DIN_DIN (0x30)
219#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
220#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]221#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]222#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
223#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]224#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]225#define GPIO_PAR_QSPI_SCK_SCK (0x03)
226#define GPIO_PAR_QSPI_SCK_SCL (0x02)
227
228#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6)
229#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
230#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
231#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]232#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]233#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
234#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
235#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]236#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]237#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
238#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
239#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]240#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]241#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
242#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
243#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]244#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]245#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
246#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
247#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
248
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]249#define GPIO_PAR_UART1_UNMASK (0xF03F)
250#define GPIO_PAR_UART0_UNMASK (0xFFC0)
251#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]252#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
253#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
254#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]255#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]256#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
257#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
258#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
259#define GPIO_PAR_UART_U1TXD (0x0080)
260#define GPIO_PAR_UART_U1RXD (0x0040)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]261#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]262#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
263#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
264#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]265#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]266#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
267#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
268#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
269#define GPIO_PAR_UART_U0TXD (0x0002)
270#define GPIO_PAR_UART_U0RXD (0x0001)
271
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]272#define GPIO_PAR_FEC_7W_UNMASK (0xF3)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]273#define GPIO_PAR_FEC_7W_FEC (0x0C)
274#define GPIO_PAR_FEC_7W_U1RTS (0x04)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]275#define GPIO_PAR_FEC_MII_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]276#define GPIO_PAR_FEC_MII_FEC (0x03)
277#define GPIO_PAR_FEC_MII_UnCTS (0x01)
278
279#define GPIO_PAR_IRQ_IRQ4 (0x01)
280
281#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6)
282#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
283#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
284#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]285#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F)
286#define GPIO_MSCR_FB_DUP_UNMASK (0xCF)
287#define GPIO_MSCR_FB_DLO_UNMASK (0xF3)
288#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]289
290#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
291#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
292#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]293#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF)
294#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3)
295#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]296
297#define MSCR_25VDDR (0x03)
298#define MSCR_18VDDR_FULL (0x02)
299#define MSCR_OPENDRAIN (0x01)
300#define MSCR_18VDDR_HALF (0x00)
301
302#define GPIO_DSCR_I2C(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]303#define GPIO_DSCR_I2C_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]304
305#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]306#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]307#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]308#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]309#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]310#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]311
312#define GPIO_DSCR_FEC(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]313#define GPIO_DSCR_FEC_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]314
315#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]316#define GPIO_DSCR_UART_UART1_UNMASK (0xCF)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]317#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]318#define GPIO_DSCR_UART_UART0_UNMASK (0xF3)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]319#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]320#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]321
322#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]323#define GPIO_DSCR_QSPI_UNMASK (0xFC)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]324
325#define DSCR_50PF (0x03)
326#define DSCR_30PF (0x02)
327#define DSCR_20PF (0x01)
328#define DSCR_10PF (0x00)
329
330/* *** Phase Locked Loop (PLL) *** */
331#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]332#define PLL_PODR_CPUDIV_UNMASK (0x0F)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]333#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]334#define PLL_PODR_BUSDIV_UNMASK (0xF0)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]335
336#define PLL_PCR_DITHEN (0x80)
337#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
TsiChung Liewbbb8ddc2010-03-09 18:32:16 -0600[diff] [blame]338#define PLL_PCR_DITHDEV_UNMASK (0xF8)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]339
340#endif /* __M520X__ */