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git01.mediatek.com / filogic / uboot / 35603fff7072a9e387bb2e3b35d7ca945310bd11 / . / board / nvidia / nyan-big / nyan-big.c
blob: ba964018901a24b3dea4c6a32c8f584acb740de5 [file] [log] [blame]
Allen Martina142ac72014-12-04 06:36:30 -0700[diff] [blame]1/*
2 * (C) Copyright 2014
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]9#include <errno.h>
10#include <asm/gpio.h>
Simon Glass899af8e2015-06-05 14:39:43 -0600[diff] [blame]11#include <asm/io.h>
Allen Martina142ac72014-12-04 06:36:30 -0700[diff] [blame]12#include <asm/arch/pinmux.h>
Simon Glass899af8e2015-06-05 14:39:43 -0600[diff] [blame]13#include <asm/arch/clock.h>
14#include <asm/arch/mc.h>
15#include <asm/arch-tegra/clk_rst.h>
16#include <asm/arch-tegra/pmc.h>
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]17#include <power/as3722.h>
18#include <power/pmic.h>
Allen Martina142ac72014-12-04 06:36:30 -0700[diff] [blame]19#include "pinmux-config-nyan-big.h"
20
21/*
22 * Routine: pinmux_init
23 * Description: Do individual peripheral pinmux configs
24 */
25void pinmux_init(void)
26{
27 gpio_config_table(nyan_big_gpio_inits,
28 ARRAY_SIZE(nyan_big_gpio_inits));
29
30 pinmux_config_pingrp_table(nyan_big_pingrps,
31 ARRAY_SIZE(nyan_big_pingrps));
32
33 pinmux_config_drvgrp_table(nyan_big_drvgrps,
34 ARRAY_SIZE(nyan_big_drvgrps));
35}
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]36
37int tegra_board_id(void)
38{
39 static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1,
40 GPIO_PX4, -1};
41
42 gpio_claim_vector(vector, "board_id%d");
43 return gpio_get_values_as_int(vector);
44}
45
46int tegra_lcd_pmic_init(int board_id)
47{
48 struct udevice *pmic;
49 int ret;
50
51 ret = as3722_get(&pmic);
52 if (ret)
53 return -ENOENT;
54
55 if (board_id == 0)
56 as3722_write(pmic, 0x00, 0x3c);
57 else
58 as3722_write(pmic, 0x00, 0x50);
59 as3722_write(pmic, 0x12, 0x10);
60 as3722_write(pmic, 0x0c, 0x07);
61 as3722_write(pmic, 0x20, 0x10);
62
63 return 0;
64}
Simon Glass899af8e2015-06-05 14:39:43 -0600[diff] [blame]65
66/* Setup required information for Linux kernel */
67static void setup_kernel_info(void)
68{
69 struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
70
71 /* The kernel graphics driver needs this region locked down */
72 writel(0, &mc->mc_video_protect_bom);
73 writel(0, &mc->mc_video_protect_size_mb);
74 writel(1, &mc->mc_video_protect_reg_ctrl);
75}
76
77/*
78 * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
79 * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
80 * Otherwise reading AHUB devices will hang when the kernel boots.
81 */
82static void enable_required_clocks(void)
83{
84 static enum periph_id ids[] = {
85 PERIPH_ID_I2S0,
86 PERIPH_ID_I2S1,
87 PERIPH_ID_I2S2,
88 PERIPH_ID_I2S3,
89 PERIPH_ID_I2S4,
90 PERIPH_ID_AUDIO,
91 PERIPH_ID_APBIF,
92 PERIPH_ID_DAM0,
93 PERIPH_ID_DAM1,
94 PERIPH_ID_DAM2,
95 PERIPH_ID_AMX0,
96 PERIPH_ID_AMX1,
97 PERIPH_ID_ADX0,
98 PERIPH_ID_ADX1,
99 PERIPH_ID_SPDIF,
100 PERIPH_ID_AFC0,
101 PERIPH_ID_AFC1,
102 PERIPH_ID_AFC2,
103 PERIPH_ID_AFC3,
104 PERIPH_ID_AFC4,
105 PERIPH_ID_AFC5,
106 PERIPH_ID_EXTPERIPH1
107 };
108 int i;
109
110 for (i = 0; i < ARRAY_SIZE(ids); i++)
111 clock_enable(ids[i]);
112 udelay(2);
113 for (i = 0; i < ARRAY_SIZE(ids); i++)
114 reset_set_enable(ids[i], 0);
115}
116
117int nvidia_board_init(void)
118{
119 clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
120 clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
121
122 /* For external MAX98090 audio codec */
123 clock_external_output(1);
124 setup_kernel_info();
125 enable_required_clocks();
126
127 return 0;
128}