blob: c61d25fbead702f9fc64a1b9bb9b1cc18391a112 [file] [log] [blame]
Adam Ford14879032020-05-03 08:11:33 -05001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6#include <common.h>
7#include <miiphy.h>
8#include <netdev.h>
9
10#include <asm/arch/clock.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/io.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
Adam Ford14879032020-05-03 08:11:33 -050016#if IS_ENABLED(CONFIG_FEC_MXC)
17static int setup_fec(void)
18{
19 struct iomuxc_gpr_base_regs *gpr =
20 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
21
22 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
23 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
24
25 return 0;
26}
27
28int board_phy_config(struct phy_device *phydev)
29{
30 /* enable rgmii rxc skew and phy mode select to RGMII copper */
31 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
32 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
33
34 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
35 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
36 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
37 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
38
39 if (phydev->drv->config)
40 phydev->drv->config(phydev);
41 return 0;
42}
43#endif
44
45int board_init(void)
46{
47 if (IS_ENABLED(CONFIG_FEC_MXC))
48 setup_fec();
49
50 return 0;
51}
52
53int board_mmc_get_env_dev(int devno)
54{
55 return devno;
56}